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mb95630h series new 8fx 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04627 rev. *a revised march 29, 2016 the mb95630h series is a series of general-purpose, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral functions. features f 2 mc-8fx cpu core ? instruction set optimized for controllers ? multiplication and division instructions ? 16-bit arithmetic operations ? bit test bran ch instructions ? bit manipulation instructions, etc. clock ? selectable main clock source ? main oscillation clock (up to 16.25 mhz, maximum ma- chine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (4 mhz ? 2%) ? main cr pll clock - the main cr pll clock frequency becomes 8 mhz ? 2% when the pll multiplication rate is 2. - the main cr pll clock frequency becomes 10 mhz ? 2% when the pll multiplication rate is 2.5. - the main cr pll clock frequency becomes 12 mhz ? 2% when the pll multiplication rate is 3. - the main cr pll clock frequency becomes 16 mhz ? 2% when the pll multiplication rate is 4. ? selectable subclock source ? suboscillation clock (32.768 khz) ? external clock (32.768 khz) ? sub-cr clock (typ: 100 khz, min: 50 khz, max: 150 khz) timer ? 8/16-bit composite timer ? 2 channels ? 8/16-bit ppg ? 3 channels ? 16-bit ppg timer ? 1 channel (can work independently or together with the mult i-pulse generator) ? 16-bit reload timer ? 1 channel (can work independently or together with the mult i-pulse generator) ? time-base timer ? 1 channel ? watch prescaler ? 1 channel uart/sio ? 1 channel ? full duplex double buffer ? capable of clock asynchronous (uart) serial data transfer and clock synchronous (sio) serial data transfer i 2 c bus interface ? 1 channel ? built-in wake-up function multi-pulse generator (mpg) (for dc motor control) ? 1 channel ? 16-bit reload timer ? 1 channel ? 16-bit ppg timer ? 1 channel ? waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear function) lin-uart ? full duplex double buffer ? capable of clock asynchronous serial data transfer and clock synchronous serial data transfer external interrupt ? 10 channels ? interrupt by edge detection (r ising edge, falling edge, and both edges can be selected) ? can be used to wake up the device from different low power consumption (standby) modes 8/10-bit a/d converter ? 8 channels ? 8-bit or 10-bit resolution can be selected. low power consumption (standby) modes ? there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode ? in standby mode, two further options can be selected: normal standby mode and deep standby mode. i/o port ? mb95f632h/f633h/f634h/f636h (number of i/o ports: 28) ? general-purpose i/o ports (cmos i/o): 25 ? general-purpose i/o ports (n-ch open drain): 3 ? mb95f632k/f633k/f634k/f636k (number of i/o ports: 29) ? general-purpose i/o ports (cmos i/o): 25 ? general-purpose i/o ports (n-ch open drain): 4 on-chip debug ? 1-wire serial control ? serial writing supported (asynchronous mode) hardware/software watchdog timer ? built-in hardware watchdog timer ? built-in software watchdog timer power-on reset ? a power-on reset is generated when the power is switched on. low-voltage detection reset circuit (only available on mb95f632k/f633k/f634k/f636k) ? built-in low-voltage detection function (the combination of detection voltage and release voltage can be selected from four options.) comparator clock supervisor counter ? built-in clock su pervisor counter dual operation flash memory ? the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simul- taneously. flash memory security function ? protects the content of the flash memory.
mb95630h series document number: 002-04627 rev. *a page 2 of 102 contents features............................................................................. 1 1. product line-up ............................................................ 3 2. packages and corresponding products.................... 5 3. differences among pr oducts and notes on product selection ............................................................. 5 4. pin assignment ............................................................ 6 5. pin functions................................................................ 8 6. i/o circuit type ........................................................... 12 7. handling precaution s............ .............. .............. ......... 14 7.1 precautions for product design........................... 14 7.2 precautions for package mounting ..................... 15 7.3 precautions for use environment........................ 17 8. notes on device handling......................................... 17 9. pin connection ........................................................... 18 10. block diagram .......................................................... 19 11. cpu core................................................................... 20 12. memory space .......................................................... 21 13. areas for specific applicat ions ...... .............. ......... 23 14. i/o map....................................................................... 24 15. i/o ports..................................................................... 30 15.1 port 0................................................................. 31 15.2 port 1................................................................. 39 15.3 port 6................................................................. 46 15.4 port f................................................................. 51 15.5 port g ................................................................ 53 16. interrupt source table ............................................. 56 17. pin states in each mode .......................................... 57 18. electrical characteristics... ...................................... 61 18.1 absolute maximum rating s............................... 61 18.2 recommended operating conditions ............... 63 18.3 dc characteristics ......... ................................... 64 18.4 ac characteristics.......... ................................... 67 18.5 a/d converter................................................... 85 18.6 flash memory program/erase characteristics.. 89 19. sample characteristics............................................ 90 20. mask options ............................................................ 97 21. ordering information................................................ 97 22. package dimension. .............. .............. .............. ....... 98 23. major changes in this edition .............................. 101 document history page .............. ................................. 101 sales, solutions, and legal information .................... 102
mb95630h series document number: 002-04627 rev. *a page 3 of 102 1. product line-up part number parameter mb95f632h mb95f633h mb95f634h mb95f636h mb95f632k mb95f633k mb95f634k mb95f636k type flash memory product clock supervisor counter it supervises the main clock osc illation and the subclock oscillation. flash memory capacity 8 kbyte 12 kbyte 20 kbyte 36 kbyte 8 kbyte 12 kbyte 20 kbyte 36 kbyte ram capacity 256 bytes 512 bytes 1024 bytes 1024 bytes 256 bytes 512 bytes 1024 bytes 1024 bytes power-on reset yes low-voltage detection reset no yes reset input dedicated selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general- purpose i/o ? i/o port : 28 ?cmos i/o :25 ? n-ch open drain : 3 ? i/o port : 29 ? cmos i/o : 25 ? n-ch open drain : 4 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be us ed as the source clock of the software watchdog timer. wild register it can be used to replace 3 bytes of data. lin-uart ? a wide range of communication speed can be selected by a dedicated reload timer. ? it has a full duplex double buffer. ? both clock synchronous serial data transfer an d clock asynchronous serial data transfer are enabled. ? the lin function can be used as a lin master or a lin slave. 8/10-bit a/d converter 8 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? it has the following functions: interval timer function, pwc function, pwm function and input capture function. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? it can output square wave.
mb95630h series document number: 002-04627 rev. *a page 4 of 102 part number parameter mb95f632h mb95f633h mb95f634h mb95f636h mb95f632k mb95f633k mb95f634k mb95f636k external interrupt 10 channels ? interrupt by edge detection (the rising edge , falling edge, and both edges can be selected.) ? it can be used to wake up the device from different standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode). uart/sio 1 channel ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-first data transfer are available to use. ? both clock asynchronous (uart) serial data transfer and clock synchronous (sio) serial data transfer are enabled. i 2 c bus interface 1 channel ? master/slave transmission and reception ? it has the following functions: bus error function, arbitration function, transfer direction de- tection function, wake-up function, and func tions of generating and detecting repeated start conditions. 8/16-bit ppg 3 channels ? each channel can be used as an ?8-bit timer ? 2 channels? or a ?16-bit timer ? 1 channel?. ? the counter operating clock can be selected from eight clock sources. 16-bit ppg timer 1 channel ? pwm mode and one-shot mode are available to use. ? the counter operating clock can be selected from eight clock sources. ? it supports external trigger start. ? it can work independently or together with the multi-pulse generator. 16-bit reload timer 1 channel ? two clock modes and two counter operating modes are available to use. ? it can output square wave. ? count clock: it can be selected from intern al clocks (seven types) and external clocks. ? two counter operating modes: reload mode and one-shot mode ? it can work independently or together with the multi-pulse generator. multi-pulse generator (for dc motor control) ? 16-bit ppg timer: 1 channel ? 16-bit reload timer operations: toggle output, one-shot output ? event counter: 1 channel ? waveform sequencer (including a 16-bit time r equipped with a buffer and a compare clear function) watch prescaler eight different time intervals can be selected. comparator 1 channel
mb95630h series document number: 002-04627 rev. *a page 5 of 102 2. packages and corresponding products ? : available 3. differences am ong products and notes on product selection ? current consumption when using the on-chip debug function, take account of the current consumption of flash memory program/erase. for details of current consumption, see ?electrical characteristics?. ? package for details of information on each package, see ?package s and corresponding products ? and ?package dimension?. ? operating voltage the operating voltage varies, depending on whet her the on-chip debug function is used or not. for details of operating voltage, see ?electrical characteristics?. ? on-chip debug function part number parameter mb95f632h mb95f633h mb95f634h mb95f636h mb95f632k mb95f633k mb95f634k mb95f636k flash memory ? it supports automatic programming (embe dded algorithm), and program/erase/erase- suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode there are four standby modes as follows: ? stop mode ? sleep mode ?watch mode ? time-base timer mode in standby mode, two further options can be selected: normal standby mode and deep standby mode. package fpt-32p-m30 dip-32p-m06 lcc-32p-m19 part number package mb95f632h mb95f633h mb95f634h mb95f636h mb95f632k mb95f633k mb95f634k mb95f636k fpt-32p-m30 ???????? dip-32p-m06 ???????? lcc-32p-m19 ???????? number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
mb95630h series document number: 002-04627 rev. *a page 6 of 102 the on-chip debug function requires that v cc , v ss and one serial wire be connected to an evaluation tool. for details of the connection method, refer to ?chapter 25 example of serial programming conn ection? in ?new 8fx mb95630h series hardware manual?. 4. pin assignment vss pf1/x1 pf0/x0 pf2/rst p17/to1/sni0 p16/ui0/ppg21 p15/uo0/ppg20 p14/uck0/ppg01 p13/ppg00 p12/dbg/ec0 p11/ppg11 p10/ppg10/cmp0_o pg2/x1a/sni2 pg1/x0a/sni1 vcc c p67/ppg21/trg1/opt5 p66/ppg20/ppg1/opt4 p65/ppg11/opt3 p64/ec1/ppg10/opt2 (top view) lqfp32 fpt-32p-m30 32 31 30 29 28 27 26 25 24 23 22 21 p07/int07/an07 p06/int06/an06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 20 19 18 17 1 2 3 4 5 6 7 8 p63/to11/ppg01/opt1 p62/to10/ppg00/opt0 p61/int09/scl/ti1 p60/int08/sda/dtti 9 10 11 12 p00/int00/an00/cmp0_p p01/int01/an01/cmp0_n p02/int02/an02/sck 13 14 15 p03/int03/an03/sot 16
mb95630h series document number: 002-04627 rev. *a page 7 of 102 p17/to1/sni0 p16/ui0/ppg21 p15/uo0/ppg20 p14/uck0/ppg01 p13/ppg00 p12/dbg/ec0 p11/ppg11 p10/ppg10/cmp0_o p07/int07/an07 p06/int06/an06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 pf2/rst pf0/x0 pf1/x1 vss pg2/x1a/sni2 pg1/x0a/sni1 vcc c p67/ppg21/trg1/opt5 p66/ppg20/ppg1/opt4 p65/ppg11/opt3 p64/ec1/ppg10/opt2 (top view) sh-dip32 dip-32p-m06 32 31 30 29 28 27 26 25 24 23 22 21 p03/int03/an03/sot p02/int02/an02/sck p01/int01/an01/cmp0_n p00/int00/an00/cmp0_p 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 p63/to11/ppg01/opt1 p62/to10/ppg00/opt0 p61/int09/scl/ti1 13 14 15 p60/int08/sda/dtti 16 vss pf1/x1 pf0/x0 pf2/rst p17/to1/sni0 p16/ui0/ppg21 p15/uo0/ppg20 p14/uck0/ppg01 p13/ppg00 p12/dbg/ec0 p11/ppg11 p10/ppg10/cmp0_o pg2/x1a/sni2 pg1/x0a/sni1 vcc c p67/ppg21/trg1/opt5 p66/ppg20/ppg1/opt4 p65/ppg11/opt3 p64/ec1/ppg10/opt2 (top view) qfn32 lcc-32p-m19 32 31 30 29 28 27 26 25 24 23 22 21 p07/int07/an07 p06/int06/an06/to01 p05/int05/an05/to00 p04/int04/an04/sin/ec0 20 19 18 17 1 2 3 4 5 6 7 8 p63/to11/ppg01/opt1 p62/to10/ppg00/opt0 p61/int09/scl/ti1 p60/int08/sda/dtti 9 10 11 12 p00/int00/an00/cmp0_p p01/int01/an01/cmp0_n p02/int02/an02/sck 13 14 15 p03/int03/an03/sot 16
mb95630h series document number: 002-04627 rev. *a page 8 of 102 5. pin functions pin no. pin name i/o circuit type* 4 function i/o type lqfp32* 1 , qfn32* 2 sh-dip32* 3 input output od* 5 pu* 6 15 pg2 c general-purpose i/o port hysteresis cmos ? ? x1a subclock i/o oscillation pin sni2 trigger input pin for the position detection function of the mpg waveform sequencer 26 pg1 c general-purpose i/o port hysteresis cmos ? ? x0a subclock input oscillation pin sni1 trigger input pin for the position detection function of the mpg waveform sequencer 37v cc ? power supply pin ???? 48c ? decoupling capacitor connection pin ???? 59 p67 d general-purpose i/o port high-current pin hysteresis cmos ? ? ppg21 8/16-bit ppg ch. 2 output pin trg1 16-bit ppg timer ch. 1 trigger input pin opt5 mpg waveform sequencer output pin 610 p66 d general-purpose i/o port high-current pin hysteresis cmos ? ? ppg20 8/16-bit ppg ch. 2 output pin ppg1 16-bit ppg timer ch. 1 output pin opt4 mpg waveform sequencer output pin 711 p65 d general-purpose i/o port high-current pin hysteresis cmos ? ? ppg11 8/16-bit ppg ch. 1 output pin opt3 mpg waveform sequencer output pin 812 p64 d general-purpose i/o port high-current pin hysteresis cmos ? ? ec1 8/16-bit composite timer ch. 1 clock input pin ppg10 8/16-bit ppg ch. 1 output pin opt2 mpg waveform sequencer output pin
mb95630h series document number: 002-04627 rev. *a page 9 of 102 pin no. pin name i/o circuit type* 4 function i/o type lqfp32* 1 , qfn32* 2 sh-dip32* 3 input output od* 5 pu* 6 913 p63 d general-purpose i/o port high-current pin hysteresis cmos ? ? to11 8/16-bit composite timer ch. 1 output pin ppg01 8/16-bit ppg ch. 0 output pin opt1 mpg waveform sequencer output pin 10 14 p62 d general-purpose i/o port high-current pin hysteresis cmos ? ? to10 8/16-bit composite timer ch. 1 output pin ppg00 8/16-bit ppg ch. 0 output pin opt0 mpg waveform sequencer output pin 11 15 p61 i general-purpose i/o port cmos cmos ? ? int09 external interrupt input pin scl i 2 c bus interface ch. 0 clock i/o pin ti1 16-bit reload timer ch. 1 input pin 12 16 p60 i general-purpose i/o port cmos cmos ? ? int08 external interrupt input pin sda i 2 c bus interface ch. 0 data i/o pin dtti mpg waveform se quencer input pin 13 17 p00 e general-purpose i/o port hysteresis/ analog cmos ? ? int00 external interrupt input pin an00 8/10-bit a/d converter analog input pin cmp0_p comparator non-inverting analog input (positive input) pin 14 18 p01 e general-purpose i/o port hysteresis/ analog cmos ? ? int01 external interrupt input pin an01 8/10-bit a/d converter analog input pin cmp0_n comparator inverting analog input (negative input) pin
mb95630h series document number: 002-04627 rev. *a page 10 of 102 pin no. pin name i/o circuit type* 4 function i/o type lqfp32* 1 , qfn32* 2 sh-dip32* 3 input output od* 5 pu* 6 15 19 p02 e general-purpose i/o port hysteresis/ analog cmos ? ? int02 external interrupt input pin an02 8/10-bit a/d converter analog input pin sck lin-uart clock i/o pin 16 20 p03 e general-purpose i/o port hysteresis/ analog cmos ? ? int03 external interrupt input pin an03 8/10-bit a/d converter analog input pin sot lin-uart data output pin 17 21 p04 f general-purpose i/o port cmos/ analog cmos ? ? int04 external interrupt input pin an04 8/10-bit a/d converter analog input pin sin lin-uart data input pin ec0 8/16-bit composite timer ch. 0 clock input pin 18 22 p05 e general-purpose i/o port hysteresis/ analog cmos ? ? int05 external interrupt input pin an05 8/10-bit a/d converter analog input pin to00 8/16-bit composite timer ch. 0 output pin 19 23 p06 e general-purpose i/o port hysteresis/ analog cmos ? ? int06 external interrupt input pin an06 8/10-bit a/d converter analog input pin to01 8/16-bit composite timer ch. 0 output pin 20 24 p07 e general-purpose i/o port hysteresis/ analog cmos ? ? int07 external interrupt input pin an07 8/10-bit a/d converter analog input pin 21 25 p10 g general-purpose i/o port hysteresis cmos ? ? ppg10 8/16-bit ppg ch. 1 output pin cmp0_o comparator digital output pin
mb95630h series document number: 002-04627 rev. *a page 11 of 102 ? : available *1: fpt-32p-m30 *2: lcc-32p-m19 *3: dip-32p-m06 *4: for the i/o circuit type s, see ?i/o circuit type?. *5: n-ch open drain *6: pull-up pin no. pin name i/o circuit type* 4 function i/o type lqfp32* 1 , qfn32* 2 sh-dip32* 3 input output od* 5 pu* 6 22 26 p11 g general-purpose i/o port hysteresis cmos ? ? ppg11 8/16-bit ppg ch. 1 output pin 23 27 p12 h general-purpose i/o port hysteresis cmos ? ? dbg dbg input pin ec0 8/16-bit composite timer ch. 0 clock input pin 24 28 p13 g general-purpose i/o port hysteresis cmos ? ? ppg00 8/16-bit ppg ch. 0 output pin 25 29 p14 g general-purpose i/o port hysteresis cmos ? ? uck0 uart/sio ch. 0 clock i/o pin ppg01 8/16-bit ppg ch. 0 output pin 26 30 p15 g general-purpose i/o port hysteresis cmos ? ? uo0 uart/sio ch. 0 data output pin ppg20 8/16-bit ppg ch. 2 output pin 27 31 p16 j general-purpose i/o port cmos cmos ? ? ui0 uart/sio ch. 0 data input pin ppg21 8/16-bit ppg ch. 2 output pin 28 32 p17 g general-purpose i/o port hysteresis cmos ? ? to1 16-bit reload timer ch. 1 output pin sni0 trigger input pin for the position detection function of the mpg waveform sequencer 29 1 pf2 a general-purpose i/o port hysteresis cmos ? ? rst reset pin dedicated reset pin on mb95f632h/f633h/f634h/ f636h 30 2 pf0 b general-purpose i/o port hysteresis cmos ?? x0 main clock input oscillation pin 31 3 pf1 b general-purpose i/o port hysteresis cmos ?? x1 main clock i/o oscillation pin 32 4 v ss ? power supply pin (gnd) ????
mb95630h series document number: 002-04627 rev. *a page 12 of 102 6. i/o circuit type type circuit remarks a ? n-ch open drain output ? hysteresis input ? reset output b ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? ? cmos output ? hysteresis input c ? oscillation circuit ? low-speed side feedback resistance: approx. 5 m ? ? cmos output ? hysteresis input ? pull-up control n-ch reset output / digital output reset input / hysteresis input standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control
mb95630h series document number: 002-04627 rev. *a page 13 of 102 type circuit remarks d ? cmos output ? hysteresis input ? pull-up control ? high current output e ? cmos output ? hysteresis input ? pull-up control ? analog input f ? cmos output ?cmos input ? pull-up control ? analog input g ? cmos output ? hysteresis input ? pull-up control h ? n-ch open drain output ? hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control hysteresis input n-ch p-ch p-ch r pull-up control digital output digital output analog input a/d control standby control cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch standby control hysteresis input digital output
mb95630h series document number: 002-04627 rev. *a page 14 of 102 7. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failu re is greatly affected by the conditions in which they are used (circuit conditions, enviro nmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability fr om your cypress semiconductor devices. 7.1 precautions for product design this section describes precautions when designing electronic equipment usin g semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (v oltage, current, temperature, etc.) in excess of certain established limits, called abso lute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warran ted when operated within these ranges. always use semiconductor devices wit hin the recommended operating conditio ns. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating condit ions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative before- hand. ? processing and protection of pins these precautions must be followed when handling the pi ns which connect semiconductor devices to power supply and input/output functions. (1) preventing over-voltage and over-current conditions exposure to voltage or current levels in excess of maxi mum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over-current conditions at the design stage. type circuit remarks i ? n-ch open drain output ?cmos input j ? cmos output ?cmos input ? pull-up control n-ch digital output standby control cmos input n-ch p-ch p-ch r pull-up control digital output digital output standby control cmos input
mb95630h series document number: 002-04627 rev. *a page 15 of 102 (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present fo r extended periods of ti me can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch-up semiconductor devices are cons tructed by the formation of p-type and n-ty pe areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junc tions (called thyristor struct ures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch-up. caution: the occurrence of latch-up not only causes lo ss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power-on sequence. ? observance of safety regulations and standards most countries in the world have established standards an d regulations regarding safety, protection from electromag- netic interference, etc. customers are requested to obse rve applicable regulations an d standards in the design of products. ? fail-safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by in corporating safety design measures into your facility and equipment su ch as redundancy, fire protection, and prevention of over-current le vels and other abnormal operating conditions. ? precautions related to usage of devices cypress semiconductor devices are intended for use in sta ndard applications (computers, office automation and other office equipment, industrial, communications, and measur ement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy co ntrols, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to co nsult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 7.2 precautions for package mounting package mounting may be either lead insertion type or surf ace mount type. in either case, for heat resistance during soldering, you should only mount under cypress?s recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed ci rcuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally in volves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applyi ng liquid solder. in this case, the soldering process usually
mb95630h series document number: 002-04627 rev. *a page 16 of 102 causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open conn ections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting tec hniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for ea ch product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. ? lead-free packaging caution: when ball grid ar ray (bga) packages with sn-ag-cu balls are mounted using sn-pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natu ral environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and ca using packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, cypress packages se miconductor devices in highly moisture -resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum lami nate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de-moistu rized by baking (heat drying). follow the cypress recom- mended conditions for baking. condition: 125c/24 h ? static electricity because semiconductor devic es are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humid ity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ? ). wearing of conductive clothing and shoes, use of conduc tive floor mats and other me asures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti-static measures. (5) avoid the use of styrofoam or ot her highly static-prone materials for storage of completed board assemblies.
mb95630h series document number: 002-04627 rev. *a page 17 of 102 7.3 precautions for use environment reliability of semiconductor devices depends on ambien t temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in de vices as well as printed circuit boards. if high humidity levels are anticipated, consider anti-humidity processing. (2) discharge of static electricity when high-voltage charges exis t close to semiconductor devices, discha rges can cause abnormal operation. in such cases, use anti-static measures or processing to prevent discharges. (3) corrosive gase s, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions th at will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are fl ammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in ot her special environmental conditions should consult with sales repres entatives. 8. notes on device handling ? preventing latch-ups when using the device, ensure that the voltage app lied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pi n, or if a voltage out of the rating range of power sup- ply voltage mentioned in ?18.1 absolute maximum ratings? of ?electrical ch aracteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. ? stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctuat es rapidly even though the fl uctuation is within the guar- anteed operating range of the v cc power supply voltage. as a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuation rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. ? notes on using the external clock when an external clock is used, oscilla tion stabilization wait time is required for power-on reset, wake-u p from sub- clock mode or stop mode.
mb95630h series document number: 002-04627 rev. *a page 18 of 102 9. pin connection ? treatment of unused pins if an unused input pin is left unconnected, a component ma y be permanently damaged due to malfunctions or latch- ups. always pull up or pull down an unused input pin through a resistor of at least 2 k ? . set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. if there is an unused outp ut pin, leave it unconnected. ? power supply pins to reduce unnecessary electro-magnetic emission, preven t malfunctions of strobe signals due to an increase in the ground level, and conform to the total out put current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addit ion, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a cera mic capacitor of approximately 0.1 f as a bypass capacitor between the v cc pin and the v ss pin at a location close to this device. ?dbg pin connect the dbg pin to an external pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not st ay at ?l? level until the reset output is released. the dbg pin becomes a communication pin in debug mode. si nce the actual pull-up resi stance depends on the tool used and the interconnection length, refer to the t ool document when selecting a pull-up resistor. ?rst pin connect the rst pin to an external pull-up resistor of 2 k ? or above. to prevent the device from unintentionally entering the rese t mode due to noise, minimize the interconnection length between a pull-up resistor and the rst pin and that between a pull-up resistor and the v cc pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after po wer-on. in addition, the reset output of the pf2/rst pin can be enabled by the rstoe bit in the sysc register, and the reset input function and the gen eral-purpo se i/o function can be selected by th e rsten bit in the sysc register. ?c pin use a ceramic capacitor or a capacitor with equivalent fr equency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, mini mize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. ? note on serial communication in serial communication, reception of wrong data may occur due to noise or other causes. therefore, design a printed c cs dbg rst ? dbg/rst /c pins connection diagram
mb95630h series document number: 002-04627 rev. *a page 19 of 102 circuit board to prevent noise from occurring. taking acco unt of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. if an error is de tected, retransmit the data. 10. block diagram reset with lvd dual operation flash with security function (36/20/12/8 kbyte) f 2 mc-8fx cpu ram (1024/512/256 bytes) oscillator circuit cr oscillator clock control on-chip debug wild register external interrupt interrupt controller lin-uart internal bus 8/16-bit composite timer ch. 0 8/10-bit a/d converter 16-bit reload timer mpg 16-bit ppg timer 8/16-bit ppg ch. 1 8/16-bit composite timer ch. 1 waveform sequencer uart/sio i 2 c bus interface ch. 0 8/16-bit ppg ch. 0 8/16-bit ppg ch. 2 port port pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 (pg2/x1a *2 ) (pg1/x0a *2 ) p02/int02 to p07/int07 external interrupt p00/int00, p01/int01, p60/int08, p61/int09 c (p02/sck) (p03/sot) (p04/sin) (p14/uck0) (p15/uo0) (p16/ui0) (p62 *3 /ppg00), p13/ppg00 (p63 *3 /ppg01), p14/ppg01 (p66 *3 /ppg20), p15/ppg20 (p67 *3 /ppg21), p16/ppg21 (p60 *1 /sda) (p61 *1 /scl) (p12 *1 /dbg) (p05/to00) (p06/to01) p12/ec0, (p04/ec0) (p00/an00 to p07/an07) (p62 *3 /to10) (p63 *3 /to11) (p64 *3 /ec1) comparator (p00/cmp0_p) (p01/cmp0_n) (p10/cmp0_o) (p61/ti1) (p17/to1) p62 *3 /opt0 to p67 *3 /opt5 p17/sni0, pg1/sni1, pg2/sni2 (p60/dtti) (p61/ti1) (p67 *3 /trg1) (p66 *3 /ppg1) p10/ppg10, (p64 *3 /ppg10) p11/ppg11, (p65 *3 /ppg11) vcc vss *1: *2: *3: p12, p60, p61 and pf2 are n-ch open drain pins. software select p62 to p67 are high-current pins. note: pins in parentheses indicate that those pins are shared among different peripheral functions.
mb95630h series document number: 002-04627 rev. *a page 20 of 102 11. cpu core ? memory space the memory space of the mb95630h series is 64 kbyte in size, and consists of an i/o area, an extended i/o area, a data area, and a program area. the memory space includes areas intended for specific purposes such as general- purpose registers and a vector table. the memory maps of the mb95630h series are shown below. ? memory maps mb95f633h/f633k mb95f634h/f634k mb95f632h/f632k i/o area access prohibited ram 256 bytes registers access prohibited extended i/o area access prohibited flash memory 4 kbyte flash memory 4 kbyte 0x0000 0x0080 0x0090 0x0100 0x0190 0x0f80 0x1000 0x2000 0xf000 0xffff i/o area access prohibited 0x0000 0x0080 0x0090 i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 0x0290 registers 0x0100 0x0200 access prohibited extended i/o area flash memory 4 kbyte 0x0f80 0x1000 0x2000 flash memory 4 kbyte 0x1000 0x2000 flash memory 4 kbyte extended i/o area 0x0f80 0x1000 access prohibited ram 512 bytes access prohibited flash memory 8 kbyte 0xe000 0xffff access prohibited 0x8000 0x2000 access prohibited 0xc000 ram 1024 bytes flash memory 16 kbyte 0x0490 0xffff mb95f636h/f636k i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 extended i/o area 0x0f80 access prohibited ram 1024 bytes flash memory 32 kbyte 0x0490 0xffff
mb95630h series document number: 002-04627 rev. *a page 21 of 102 12. memory space the memory space of the mb95630h series is 64 kbyte in size, and consists of an i/o area, an extended i/o area, a data area, and a program area. the memory space includes areas for specific applications such as general-pur- pose registers and a vector table. ? i/o area (addresses: 0x0000 to 0x007f) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the i/o area forms part of the memory space, it can be accessed in the same way as the memory. it can also be accessed at high-speed by using direct addressing instructions. ? extended i/o area (addresses: 0x0f80 to 0x0fff) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the extended i/o area forms part of the memory space, it can be accessed in the same way as the memory. ? data area ? static ram is incorporated in the data area as the internal data area. ? the internal ram size varies according to product. ? the ram area from 0x0090 to 0x00ff can be accessed at high-speed by using dire ct addressing instructions. ? in mb95f636h/f636k, the area from 0x0090 to 0x047f is an extended direct addressing area. it can be accessed at high-speed by direct addressing instru ctions with a direct bank pointer set. ? in mb95f634h/f634k, the area from 0x0090 to 0x047f is an extended direct addressing area. it can be accessed at high-speed by direct addressing instru ctions with a direct bank pointer set. ? in mb95f633h/f633k, the area from 0x0090 to 0x028f is an extended direct addressing area. it can be accessed at high-speed by direct addressing instru ctions with a direct bank pointer set. ? in mb95f632h/f632k, the area from 0x0090 to 0x018f is an extended direct addressing area. it can be accessed at high-speed by direct addressing instru ctions with a direct bank pointer set. ? in mb95f633h/f633k/f634h/f634k/f636h/f636k, the area from 0x0100 to 0x01ff can be used as a general- purpose register area. ? in mb95f632h/f632k, the area from 0x0100 to 0x018f can be used as a general-purpose register area. ? program area ? the flash memory is incorporated in the program area as the internal program area. ? the flash memory size varies according to product. ? the area from 0xffc0 to 0xffff is used as the vector table. ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register.
mb95630h series document number: 002-04627 rev. *a page 22 of 102 ? memory space map direct addressing area extended direct addressing area i/o area access prohibited 0x0000 0x0080 0x0090 registers (general-purpose register area) 0x0100 0x0200 0x047f vector table area extended i/o area 0x0f80 0x0fff 0x1000 access prohibited program area data area 0x048f 0x0490 0xffff 0xffc0
mb95630h series document number: 002-04627 rev. *a page 23 of 102 13. areas for spec ific applications the general-purpose register area and vector tabl e area are used for the specific applications. ? general-purpose register area (addresses: 0x0100 to 0x01ff* 1 ) ? this area contains the auxiliary registers used fo r 8-bit arithmetic opera tions, transfer, etc. ? as this area forms part of the ram area, it can also be used as conventional ram. ? when the area is used as general-pur pose registers, general-purpose regist er addressing enables high-speed ac- cess with short instructions. ? non-volatile register data area (addresses: 0xffbb to 0xffbf) ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register. for details, refer to ?chapter 26 non-volatile register (nvr) interface? in ?new 8fx mb95630h series hardware manual?. ? vector table area (addresses: 0xffc0 to 0xffff) ? this area is used as the vector table for vector call instructions (callv), interrupts, and resets. ? the top of the flash memory area is allocated to the vect or table area. the start address of a service routine is set to an address in the vector table in the form of data. ?interrupt source table? lists the vect or table addresses corresponding to vector call instructions, interrupts, and re- sets. for details, refer to ?chapter 4 reset?, ?chapt er 5 interrupts? and ?a.2 special instruction special in- struction callv #vct? in ?new 8fx mb95630h series hardware manual?. ? direct bank pointer and access area *1: due to the memory size limit, the available a ccess area is up to ?0x018f? in mb95f632h/f632k. *2: due to the memory size limit, the available a ccess area is up to ?0x028f? in mb95f633h/f633k. direct bank pointer (dp[2:0]) operand-specified dir access area 0bxxx (it does not affect mapping. ) 0x0000 to 0x007f 0x0000 to 0x007f 0b000 (initial value) 0x0090 to 0x00ff 0x0090 to 0x00ff 0b001 0x0080 to 0x00ff 0x0100 to 0x017f 0b010 0x0180 to 0x01ff* 1 0b011 0x0200 to 0x027f 0b100 0x0280 to 0x02ff* 2 0b101 0x0300 to 0x037f 0b110 0x0380 to 0x03ff 0b111 0x0400 to 0x047f
mb95630h series document number: 002-04627 rev. *a page 24 of 102 14. i/o map address register abbreviation register name r/w initial value 0x0000 pdr0 port 0 data register r/w 0b00000000 0x0001 ddr0 port 0 directio n register r/w 0b00000000 0x0002 pdr1 port 1 data register r/w 0b00000000 0x0003 ddr1 port 1 directio n register r/w 0b00000000 0x0004 ? (disabled) ? ? 0x0005 watr oscillation stabilization wait time setting register r/w 0b11111111 0x0006 pllc pll control register r/w 0b000x0000 0x0007 sycc system clock cont rol register r/w 0bxxx11011 0x0008 stbc standby control register r/w 0b00000000 0x0009 rsrr reset source register r/w 0b000xxxxx 0x000a tbtc time-base timer control register r/w 0b00000000 0x000b wpcr watch prescaler control register r/w 0b00000000 0x000c wdtc watchdog timer control register r/w 0b00xx0000 0x000d sycc2 system clock control register 2 r/w 0bxxxx0011 0x000e stbc2 standby control register 2 r/w 0b00000000 0x000f to 0x0015 ? (disabled) ? ? 0x0016 pdr6 port 6 data register r/w 0b00000000 0x0017 ddr6 port 6 directio n register r/w 0b00000000 0x0018 to 0x0027 ? (disabled) ? ? 0x0028 pdrf port f data register r/w 0b00000000 0x0029 ddrf port f direction register r/w 0b00000000 0x002a pdrg port g data register r/w 0b00000000 0x002b ddrg port g direction register r/w 0b00000000 0x002c pul0 port 0 pull-up register r/w 0b00000000 0x002d pul1 port 1 pull-up register r/w 0b00000000 0x002e to 0x0032 ? (disabled) ? ? 0x0033 pul6 port 6 pull-up register r/w 0b00000000 0x0034 ? (disabled) ? ? 0x0035 pulg port g pull-up register r/w 0b00000000 0x0036 t01cr1 8/16-bit composite timer 01 status control register 1 r/w 0b00000000
mb95630h series document number: 002-04627 rev. *a page 25 of 102 address register abbreviation register name r/w initial value 0x0037 t00cr1 8/16-bit composite timer 00 status control register 1 r/w 0b00000000 0x0038 t11cr1 8/16-bit composite timer 11 status control register 1 r/w 0b00000000 0x0039 t10cr1 8/16-bit composite timer 10 status control register 1 r/w 0b00000000 0x003a pc01 8/16-bit ppg timer 01 control register r/w 0b00000000 0x003b pc00 8/16-bit ppg timer 00 control register r/w 0b00000000 0x003c pc11 8/16-bit ppg timer 11 control register r/w 0b00000000 0x003d pc10 8/16-bit ppg timer 10 control register r/w 0b00000000 0x003e pc21 8/16-bit ppg timer 21 control register r/w 0b00000000 0x003f pc20 8/16-bit ppg timer 20 control register r/w 0b00000000 0x0040 tmcsrh1 16-bit reload timer control status register (upper) r/w 0b00000000 0x0041 tmcsrl1 16-bit reload timer control status register (lower) r/w 0b00000000 0x0042 cmr0c comparator control register r/w 0b00000101 0x0043 ? (disabled) ? ? 0x0044 pcnth1 16-bit ppg status control register (upper) r/w 0b00000000 0x0045 pcntl1 16-bit ppg status cont rol register (lower) r/w 0b00000000 0x0046, 0x0047 ? (disabled) ? ? 0x0048 eic00 external interrupt circuit control register ch. 0/ch. 1 r/w 0b00000000 0x0049 eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 0b00000000 0x004a eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 0b00000000 0x004b eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 0b00000000 0x004c eic01 external interrupt circuit control register ch. 8/ch. 9 r/w 0b00000000 0x004d ? (disabled) ? ? 0x004e lvdr lvd reset voltage selection id register r/w 0b00000000 0x004f ? (disabled) ? ? 0x0050 scr lin-uart serial co ntrol register r/w 0b00000000 0x0051 smr lin-uart serial mode register r/w 0b00000000 0x0052 ssr lin-uart serial status register r/w 0b00001000 0x0053 rdr lin-uart receive data register r/w 0b00000000 tdr lin-uart transmit data register 0x0054 escr lin-uart extended status control register r/w 0b00000100 0x0055 eccr lin-uart extended communica tion control register r/w 0b000000xx 0x0056 smc10 uart/sio serial mode control register 1 r/w 0b00000000 0x0057 smc20 uart/sio serial mode control register 2 r/w 0b00100000 0x0058 ssr0 uart/sio serial status and data register r/w 0b00000001 0x0059 tdr0 uart/sio serial output data register r/w 0b00000000
mb95630h series document number: 002-04627 rev. *a page 26 of 102 address register abbreviation register name r/w initial value 0x005a rdr0 uart/sio serial in put data register r 0b00000000 0x005b to 0x005f ? (disabled) ? ? 0x0060 ibcr00 i 2 c bus control register 0 ch. 0 r/w 0b00000000 0x0061 ibcr10 i 2 c bus control register 1 ch. 0 r/w 0b00000000 0x0062 ibsr0 i 2 c bus status register ch. 0 r/w 0b00000000 0x0063 iddr0 i 2 c data register ch. 0 r/w 0b00000000 0x0064 iaar0 i 2 c address register ch. 0 r/w 0b00000000 0x0065 iccr0 i 2 c clock control register ch. 0 r/w 0b00000000 0x0066 opcur 16-bit mpg output control register (upper) r/w 0b00000000 0x0067 opclr 16-bit mpg output control register (lower) r/w 0b00000000 0x0068 ipcur 16-bit mpg input control register (upper) r/w 0b00000000 0x0069 ipclr 16-bit mpg input control register (lower) r/w 0b00000000 0x006a nccr 16-bit mpg noise cancellation control register r/w 0b00000000 0x006b tcsr 16-bit mpg timer cont rol status register r/w 0b00000000 0x006c adc1 8/10-bit a/d converter control register 1 r/w 0b00000000 0x006d adc2 8/10-bit a/d converter control register 2 r/w 0b00000000 0x006e addh 8/10-bit a/d converter data register (upper) r/w 0b00000000 0x006f addl 8/10-bit a/d converter data register (lower) r/w 0b00000000 0x0070 ? (disabled) ? ? 0x0071 fsr2 flash memory stat us register 2 r/w 0b00000000 0x0072 fsr flash memory status register r/w 0b000x0000 0x0073 swre0 flash memory sector wr ite control register 0 r/w 0b00000000 0x0074 fsr3 flash memory st atus register 3 r 0b000xxxxx 0x0075 fsr4 flash memory stat us register 4 r/w 0b00000000 0x0076 wren wild register address compare enable register r/w 0b00000000 0x0077 wror wild register data test setting register r/w 0b00000000 0x0078 ? mirror of register bank pointer (rp) and direct bank pointer (dp) ?? 0x0079 ilr0 interrupt level setting register 0 r/w 0b11111111 0x007a ilr1 interrupt level setting register 1 r/w 0b11111111 0x007b ilr2 interrupt level setting register 2 r/w 0b11111111 0x007c ilr3 interrupt level setting register 3 r/w 0b11111111 0x007d ilr4 interrupt level setting register 4 r/w 0b11111111 0x007e ilr5 interrupt level setting register 5 r/w 0b11111111 0x007f ? (disabled) ? ?
mb95630h series document number: 002-04627 rev. *a page 27 of 102 address register abbreviation register name r/w initial value 0x0f80 wrarh0 wild register address sett ing register (upper) ch. 0 r/w 0b00000000 0x0f81 wrarl0 wild register address setting register (lower) ch. 0 r/w 0b00000000 0x0f82 wrdr0 wild register data setting register ch. 0 r/w 0b00000000 0x0f83 wrarh1 wild register address sett ing register (upper) ch. 1 r/w 0b00000000 0x0f84 wrarl1 wild register address setting register (lower) ch. 1 r/w 0b00000000 0x0f85 wrdr1 wild register data setting register ch. 1 r/w 0b00000000 0x0f86 wrarh2 wild register address sett ing register (upper) ch. 2 r/w 0b00000000 0x0f87 wrarl2 wild register address setting register (lower) ch. 2 r/w 0b00000000 0x0f88 wrdr2 wild register data setting register ch. 2 r/w 0b00000000 0x0f89 to 0x0f91 ? (disabled) ? ? 0x0f92 t01cr0 8/16-bit composite timer 01 status control register 0 r/w 0b00000000 0x0f93 t00cr0 8/16-bit composite timer 00 status control register 0 r/w 0b00000000 0x0f94 t01dr 8/16-bit composite timer 01 data register r/w 0b00000000 0x0f95 t00dr 8/16-bit composite timer 00 data register r/w 0b00000000 0x0f96 tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 0b00000000 0x0f97 t11cr0 8/16-bit composite timer 11 status control register 0 r/w 0b00000000 0x0f98 t10cr0 8/16-bit composite timer 10 status control register 0 r/w 0b00000000 0x0f99 t11dr 8/16-bit composite timer 11 data register r/w 0b00000000 0x0f9a t10dr 8/16-bit composite time r 10 data register r/w 0b00000000 0x0f9b tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 0b00000000 0x0f9c pps01 8/16-bit ppg01 cycle se tting buffer register r/w 0b11111111 0x0f9d pps00 8/16-bit ppg00 cycle se tting buffer register r/w 0b11111111 0x0f9e pds01 8/16-bit ppg01 duty setting buffer register r/w 0b11111111 0x0f9f pds00 8/16-bit ppg00 duty setting buffer register r/w 0b11111111 0x0fa0 pps11 8/16-bit ppg11 cycle sett ing buffer register r/w 0b11111111 0x0fa1 pps10 8/16-bit ppg10 cycle se tting buffer register r/w 0b11111111 0x0fa2 pds11 8/16-bit ppg11 duty setting buffer register r/w 0b11111111 0x0fa3 pds10 8/16-bit ppg10 duty setting buffer register r/w 0b11111111 0x0fa4 ppgs 8/16-bit ppg start register r/w 0b00000000 0x0fa5 revc 8/16-bit ppg output inversion register r/w 0b00000000 0x0fa6 pps21 8/16-bit ppg21 cycle se tting buffer register r/w 0b11111111 0x0fa7 pps20 8/16-bit ppg20 cycle se tting buffer register r/w 0b11111111
mb95630h series document number: 002-04627 rev. *a page 28 of 102 address register abbreviation register name r/w initial value 0x0fa8 tmrh1 16-bit reload timer timer register (upper) r/w 0b00000000 tmrlrh1 16-bit reload timer reload register (upper) 0x0fa9 tmrl1 16-bit reload timer timer register (lower) r/w 0b00000000 tmrlrl1 16-bit reload timer reload register (lower) 0x0faa pds21 8/16-bit ppg21 duty setting buffer register r/w 0b11111111 0x0fab pds20 8/16-bit ppg20 duty setting buffer register r/w 0b11111111 0x0fac to 0x0faf ? (disabled) ? ? 0x0fb0 pdcrh1 16-bit ppg downcounter register (upper) r 0b00000000 0x0fb1 pdcrl1 16-bit ppg downcounter register (lower) r 0b00000000 0x0fb2 pcsrh1 16-bit ppg cycle setting buffer register (upper) r/w 0b11111111 0x0fb3 pcsrl1 16-bit ppg cycle setting buffer register (lower) r/w 0b11111111 0x0fb4 pduth1 16-bit ppg duty setting buffer register (upper) r/w 0b11111111 0x0fb5 pdutl1 16-bit ppg duty setting buffer register (lower) r/w 0b11111111 0x0fb6 to 0x0fbb ? (disabled) ? ? 0x0fbc bgr1 lin-uart baud rate generator register 1 r/w 0b00000000 0x0fbd bgr0 lin-uart baud rate generator register 0 r/w 0b00000000 0x0fbe pssr0 uart/sio dedicated baud rate generator prescaler select register r/w 0b00000000 0x0fbf brsr0 uart/sio dedicated baud rate generator baud rate setting register r/w 0b00000000 0x0fc0 to 0x0fc2 ? (disabled) ? ? 0x0fc3 aidrl a/d input disable register (lower) r/w 0b00000000 0x0fc4 opdbrh0 16-bit mpg output data buffer register (upper) ch. 0 r/w 0b00000000 0x0fc5 opdbrl0 16-bit mpg output data buffer register (lower) ch. 0 r/w 0b00000000 0x0fc6 opdbrh1 16-bit mpg output data buffer register (upper) ch. 1 r/w 0b00000000 0x0fc7 opdbrl1 16-bit mpg output data buffer register (lower) ch. 1 r/w 0b00000000 0x0fc8 opdbrh2 16-bit mpg output data buffer register (upper) ch. 2 r/w 0b00000000 0x0fc9 opdbrl2 16-bit mpg output data buffer register (lower) ch. 2 r/w 0b00000000 0x0fca opdbrh3 16-bit mpg output data buffer register (upper) ch. 3 r/w 0b00000000 0x0fcb opdbrl3 16-bit mpg output data buffer register (lower) ch. 3 r/w 0b00000000 0x0fcc opdbrh4 16-bit mpg output data buffer register (upper) ch. 4 r/w 0b00000000 0x0fcd opdbrl4 16-bit mpg output data buffer register (lower) ch. 4 r/w 0b00000000
mb95630h series document number: 002-04627 rev. *a page 29 of 102 address register abbreviation register name r/w initial value 0x0fce opdbrh5 16-bit mpg output data buffer register (upper) ch. 5 r/w 0b00000000 0x0fcf opdbrl5 16-bit mpg output data buffer register (lower) ch. 5 r/w 0b00000000 0x0fd0 opdbrh6 16-bit mpg output data buffer register (upper) ch. 6 r/w 0b00000000 0x0fd1 opdbrl6 16-bit mpg output data buffer register (lower) ch. 6 r/w 0b00000000 0x0fd2 opdbrh7 16-bit mpg output data buffer register (upper) ch. 7 r/w 0b00000000 0x0fd3 opdbrl7 16-bit mpg output data buffer register (lower) ch. 7 r/w 0b00000000 0x0fd4 opdbrh8 16-bit mpg output data buffer register (upper) ch. 8 r/w 0b00000000 0x0fd5 opdbrl8 16-bit mpg output data buffer register (lower) ch. 8 r/w 0b00000000 0x0fd6 opdbrh9 16-bit mpg output data buffer register (upper) ch. 9 r/w 0b00000000 0x0fd7 opdbrl9 16-bit mpg output data buffer register (lower) ch. 9 r/w 0b00000000 0x0fd8 opdbrha 16-bit mpg output data buffer register (upper) ch. a r/w 0b00000000 0x0fd9 opdbrla 16-bit mpg output data buffer register (lower) ch. a r/w 0b00000000 0x0fda opdbrhb 16-bit mpg output data buffer register (upper) ch. b r/w 0b00000000 0x0fdb opdbrlb 16-bit mpg output data buffer register (lower) ch. b r/w 0b00000000 0x0fdc opdur 16-bit mpg output da ta register (upper) r 0b0000xxxx 0x0fdd opdlr 16-bit mpg output data register (lower) r 0bxxxxxxxx 0x0fde cpcur 16-bit mpg compare cl ear register ( upper) r/w 0bxxxxxxxx 0x0fdf cpclr 16-bit mpg compare cl ear register (lower) r/w 0bxxxxxxxx 0x0fe0, 0x0fe1 ? (disabled) ? ? 0x0fe2 tmbur 16-bit mpg timer bu ffer register (upper) r 0bxxxxxxxx 0x0fe3 tmblr 16-bit mpg timer bu ffer register (lower) r 0bxxxxxxxx 0x0fe4 crth main cr clock trimmi ng register (u pper) r/w 0b000xxxxx 0x0fe5 crtl main cr clock trimmi ng register (lower) r/w 0b000xxxxx 0x0fe6 ? (disabled) ? ? 0x0fe7 crtda main cr clock temperature dependent adjustment register r/w 0b000xxxxx 0x0fe8 sysc system configurat ion register r/w 0b11000011 0x0fe9 cmcr clock monitoring control register r/w 0b00000000 0x0fea cmdr clock monitoring data register r 0b00000000 0x0feb wdth watchdog timer selecti on id register (upper) r 0bxxxxxxxx 0x0fec wdtl watchdog timer selecti on id register (lower) r 0bxxxxxxxx 0x0fed, 0x0fee ? (disabled) ? ? 0x0fef wicr interrupt pin selection circuit control register r/w 0b01000000 0x0ff0 to 0x0fff ? (disabled) ? ?
mb95630h series document number: 002-04627 rev. *a page 30 of 102 ? r/w access symbols ? initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. 15. i/o ports ? list of port registers r/w : readable/writable (the read value is the same as the write value.) r, rm/w : readable/writable (the read value is different fr om the write value. the write value is read by the read- modify-write (rmw) type of instruction.) r/w : readable/writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined. register name read/write initial value port 0 data register pdr0 r, rm/w 0b00000000 port 0 direction register ddr0 r/w 0b00000000 port 1 data register pdr1 r, rm/w 0b00000000 port 1 direction register ddr1 r/w 0b00000000 port 6 data register pdr6 r, rm/w 0b00000000 port 6 direction register ddr6 r/w 0b00000000 port f data register pdrf r, rm/w 0b00000000 port f direction r egister ddrf r/w 0b00000000 port g data register pdrg r, rm/w 0b00000000 port g direction register ddrg r/w 0b00000000 port 0 pull-up register pul0 r/w 0b00000000 port 1 pull-up register pul1 r/w 0b00000000 port 6 pull-up register pul6 r/w 0b00000000 port g pull-up register pulg r/w 0b00000000 a/d input disable register (lower) aidrl r/w 0b00000000
mb95630h series document number: 002-04627 rev. *a page 31 of 102 15.1 port 0 port 0 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95630h series hardware manual?. 15.1.1 port 0 configuration port 0 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 0 data register (pdr0) ? port 0 direction register (ddr0) ? port 0 pull-up register (pul0) ? a/d input disable register (lower) (aidrl) 15.1.2 block diagrams of port 0 ? p00/int00/an00/cmp0_p pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int00) ? 8/10-bit a/d converter analog input pin (an00) ? comparator non-inverting analog input (positive input) pin (cmp0_p) ? p01/int01/an01/cmp0_n pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int01) ? 8/10-bit a/d converter analog input pin (an01) ? comparator inverting analog input (negative input) pin (cmp0_n)
mb95630h series document number: 002-04627 rev. *a page 32 of 102 ? block diagram of p00/int00/an00/cmp0_p and p01/int01/an01/cmp0_n pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction internal bus ddr0 read ddr0 write pul0 read pul0 write aidrl read aidrl write ddr0 pul0 aidrl 0 1 stop mode, watch mode (spl = 1) comparator analog input comparator analog input disable peripheral function input peripheral function input enable (int00 and int01) a/d analog input hysteresis pull-up
mb95630h series document number: 002-04627 rev. *a page 33 of 102 ? p02/int02/an02/sck pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int02) ? 8/10-bit a/d converter analog input pin (an02) ? lin-uart clock i/o pin (sck) ? p03/int03/an03/sot pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int03) ? 8/10-bit a/d converter analog input pin (an03) ? lin-uart data output pin (sot) ? p05/int05/an05/to00 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int05) ? 8/10-bit a/d converter analog input pin (an05) ? 8/16-bit composite timer ch. 0 output pin (to00) ? p06/int06/an06/to01 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int06) ? 8/10-bit a/d converter analog input pin (an06) ? 8/16-bit composite timer ch. 0 output pin (to01)
mb95630h series document number: 002-04627 rev. *a page 34 of 102 ? block diagram of p02/int02/an02/sck, p03/int03/an03/ sot, p05/int05/an05/to00 and p06/int06/an06/to01 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write aidrl read aidrl write ddr0 pul0 aidrl 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int02, int03, int05 and int06) peripheral function output enable peripheral function output a/d analog input hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 35 of 102 ? p04/int04/an04/sin/ec0 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int04) ? 8/10-bit a/d converter analog input pin (an04) ? lin-uart data input pin (sin) ? 8/16-bit composite timer ch. 0 clock input pin (ec0) ? block diagram of p04/int04/an04/sin/ec0 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write aidrl read aidrl write ddr0 pul0 aidrl 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int04) a/d analog input cmos pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 36 of 102 ? p07/int07/an07 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int07) ? 8/10-bit a/d converter analog input pin (an07) ? block diagram of p07/int07/an07 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write pul0 read pul0 write aidrl read aidrl write ddr0 pul0 aidrl 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int07) a/d analog input hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 37 of 102 15.1.3 port 0 registers ? port 0 register functions ? correspondence between registers and pins for port 0 15.1.4 port 0 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 0 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr0 register to external pins. ? if data is written to the pdr0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr0 register returns the pdr0 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr0 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when using a pin shared with the analog input function as an input port, set the corresponding bit in the a/d input disable register (lower) (aidrl) to ?1?. ? if data is written to the pdr0 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr0 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr0 register, th e pdr0 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr0 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr0 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr0 register, the pdr0 register value is returned. register abbreviation data read read by read-modify-write (rmw) instruction write pdr0 0 pin state is ?l? level. pdr0 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr0 value is ?1?. as output port, outputs ?h? level. ddr0 0 port input enabled 1 port output enabled pul0 0 pull-up disabled 1 pull-up enabled aidrl 0 analog input enabled 1 port input enabled correspondence between related register bits and pins pin name p07 p06 p05 p04 p03 p02 p01 p00 pdr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr0 pul0 aidrl
mb95630h series document number: 002-04627 rev. *a page 38 of 102 ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr0 regi ster corresponding to the input pin of a peripheral function to ?0?. ? when using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the aidrl register corresponding to that pin to ?1?. ? reading the pdr0 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr0 register, the pdr0 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr0 r egister are initialized to ?0 ? and port input is enabled . as for a pin shared with analog input, its port input is disabled becaus e the aidrl register is initialized to ?0?. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr0 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input is enabled for the external interrupt (int00 to int07), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation as an analog input pin ? set the bit in the ddr0 register bit corr esponding to the analog in put pin to ?0? and the bit corresponding to that pin in the aidrl register to ?0?. ? for a pin shared with other peripheral functions, disable th e output of such peripheral f unctions. in addition, set the corresponding bit in the pul0 register to ?0?. ? operation as an external interrupt input pin ? set the bit in the ddr0 register correspondin g to the external inte rrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt ci rcuit. when using a pin for a function other than the interrupt, disable the external interrupt fu nction corresponding to that pin. ? operation of the pull-up register setting the bit in the pul0 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul0 register. ? operation as a comparator input pin (only for p00 and p01) ? set the bit in the aidrl register corresponding to the comparator input pin to ?0?. ? regardless of the value of t he pdr0 register and that of the ddr0 regist er, if the comparator analog input enable bit in the comparator control register (cmr0c:vcid) is set to ?0?, the comparator input function is enabled. ? to disable the comparator input function, set the vcid bit to ?1?. ? for details of the comparator, refer to ?chapter 27 comparator? in ?new 8fx mb95630h series hardware manual?.
mb95630h series document number: 002-04627 rev. *a page 39 of 102 15.2 port 1 port 1 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95630h series hardware manual?. 15.2.1 port 1 configuration port 1 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 1 data register (pdr1) ? port 1 direction register (ddr1) ? port 1 pull-up register (pul1) 15.2.2 block diagrams of port 1 ? p10/ppg10/cmp0_o pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 1 output pin (ppg10) ? comparator digital output pin (cmp0_o) ? p11/ppg11 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 1 output pin (ppg11) ? p13/ppg00 pin this pin has the following peripheral function: ? 8/16-bit ppg ch. 0 output pin (ppg00) ? p15/uo0/ppg20 pin this pin has the following peripheral functions: ? uart/sio ch. 0 data output pin (uo0) ? 8/16-bit ppg ch. 2 output pin (ppg20)
mb95630h series document number: 002-04627 rev. *a page 40 of 102 ? block diagram of p10/ppg10/cmp0_o, p1 1/ppg11, p13/ppg00 and p15/uo0/ppg20 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 41 of 102 ? p12/dbg/ec0 pin this pin has the following peripheral functions: ? dbg input pin (dbg) ? 8/16-bit composite timer ch. 0 clock input pin (ec0) ? block diagram of p12/dbg/ec0 ? p14/uck0/ppg01 pin this pin has the following peripheral functions: ? uart/sio ch. 0 clock i/o pin (uck0) ? 8/16-bit ppg ch. 0 output pin (ppg01) pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 stop mode, watch mode (spl = 1) od hysteresis internal bus peripheral function input
mb95630h series document number: 002-04627 rev. *a page 42 of 102 ? block diagram of p14/uck0/ppg01 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 43 of 102 ? p16/ui0/ppg21 pin this pin has the following peripheral functions: ? uart/sio ch. 0 data input pin (ui0) ? 8/16-bit ppg ch. 2 output pin (ppg21) ? block diagram of p16/ui0/ppg21 ? p17/to1/sni0 pin this pin has the following peripheral functions: ? 16-bit reload timer ch. 1 output pin (to1) ? trigger input pin for the position detection function of the mpg waveform sequencer (sni0) pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output cmos pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 44 of 102 ? block diagram of p17/to1/sni0 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function input peripheral function output hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 45 of 102 15.2.3 port 1 registers ? port 1 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 1 *: though p12 has no pull-up function, bi t2 in the pul1 register can still be a ccessed. the operation of p12 is not af- fected by the setting of bit2 in the pul1 register. 15.2.4 port 1 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 1 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr1 register to external pins. ? if data is written to the pdr1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr1 register returns the pdr1 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr1 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr1 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr1 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr1 register, th e pdr1 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr1 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr1 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr1 register, the pdr1 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr1 regi ster corresponding to the input pin of a peripheral function register abbreviation data read read by read-modify-write (rmw) instruction write pdr1 0 pin state is ?l? level. pdr1 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr1 value is ?1?. as output port, outputs ?h? level.* ddr1 0 port input enabled 1 port output enabled pul1 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name p17 p16 p15 p14 p13 p12 p11 p10 pdr1 bit7 bit6 bit5 bit4 bit3 bit2* bit1 bit0 ddr1 pul1
mb95630h series document number: 002-04627 rev. *a page 46 of 102 to ?0?. ? reading the pdr1 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr1 register, the pdr1 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr1 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr1 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input of p14/uck0 and p16/ui0 is e nabled by the external interrupt control register ch. 0 (eic00) of the external interr upt circuit and the interrupt pin selection circ uit control register (wicr) of the interrupt pin selection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul1 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul1 register. 15.3 port 6 port 6 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95630h series hardware manual?. 15.3.1 port 6 configuration port 6 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 6 data register (pdr6) ? port 6 direction register (ddr6) ? port 6 pull-up register (pul6) 15.3.2 block diagrams of port 6 ? p60/int08/sda/dtti pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int08) ?i 2 c bus interface ch. 0 data i/o pin (sda) ? mpg waveform sequencer input pin (dtti) ? p61/int09/scl/ti1 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int09) ?i 2 c bus interface ch. 0 clock i/o pin (scl) ? 16-bit reload timer ch. 1 input pin (ti1)
mb95630h series document number: 002-04627 rev. *a page 47 of 102 ? block diagram of p60/int08/sda/dtti and p61/int09/scl/ti1 ? p62/to10/ppg00/opt0 pin this pin has the following peripheral functions: ? 8/16-bit composite timer ch. 1 output pin (to10) ? 8/16-bit ppg ch. 0 output pin (ppg00) ? mpg waveform sequencer output pin (opt0) ? p63/to11/ppg01/opt1 pin this pin has the following peripheral functions: ? 8/16-bit composite timer ch. 1 output pin (to11) ? 8/16-bit ppg ch. 0 output pin (ppg01) ? mpg waveform sequencer output pin (opt1) ? p65/ppg11/opt3 pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 1 output pin (ppg11) ? mpg waveform sequencer output pin (opt3) ? p66/ppg20/ppg1/opt4 pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 2 output pin (ppg20) ? 16-bit ppg timer ch. 1 output pin (ppg1) ? mpg waveform sequencer output pin (opt4) ? block diagram of p62/to10/ppg00/opt0, p6 3/to11/ppg01/opt1, p65/ppg11/opt3 and pdr6 pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write ddr6 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int08 and int09) peripheral function output enable peripheral function output cmos pin od internal bus
mb95630h series document number: 002-04627 rev. *a page 48 of 102 p66/ppg20/ppg1/opt4 ? p64/ec1/ppg10/opt2 pin this pin has the following peripheral functions: ? 8/16-bit composite timer ch. 1 clock input pin (ec1) ? 8/16-bit ppg ch. 1 output pin (ppg10) ? mpg waveform sequencer output pin (opt2) ? p67/ppg21/trg1/opt5 pin this pin has the following peripheral functions: ? 8/16-bit ppg ch. 2 output pin (ppg21) ? 16-bit ppg timer ch. 1 trigger input pin (trg1) ? mpg waveform sequencer output pin (opt5) pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write pul6 read pul6 write ddr6 pul6 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 49 of 102 ? block diagram of p64/ec1/ppg10/opt2 and p67/ppg21/trg1/opt5 15.3.3 port 6 registers ? port 6 register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port 6 register abbreviation data read read by read-modify-write (rmw) instruction write pdr6 0 pin state is ?l? level. pdr6 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr6 value is ?1?. as output port, outputs ?h? level.* ddr6 0 port input enabled 1 port output enabled pul6 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name p67 p66 p65 p64 p63 p62 p61 p60 pdr6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr6 pul6 -- pdr6 pin pdr6 read pdr6 write executing bit manipulation instruction ddr6 read ddr6 write pul6 read pul6 write ddr6 pul6 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 50 of 102 15.3.4 port 6 operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr 6 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdr6 register to external pins. ? if data is written to the pdr6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr6 register returns the pdr6 register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddr6 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr6 register, the value is stored in the output latch but is no t output to the pin set as an input port. ? reading the pdr6 register returns the pin value. however, if the read-modify-write (r mw) type of instruction is used to read the pdr6 register, th e pdr6 register va lue is returned. ? operation as a peripheral function output pin ? a pin becomes a peripheral function ou tput pin if the peripheral output func tion is enabled by setting the output enable bit of a peripheral functi on corresponding to that pin. ? the pin value can be read from the pdr6 register even if the peripheral function output is enabled. therefore, the output value of a peripheral function can be read by the r ead operation on the pdr6 register. however, if the read- modify-write (rmw) type of instruction is used to read the pdr6 register, the pdr6 register value is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr6 regi ster corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr6 register returns the pin value, regardless of whether the peripheral func tion uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to re ad the pdr6 register, the pdr6 register value is returned. ? operation at reset if the cpu is reset, all bits in the ddr6 register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compul sorily made to enter th e high impedance state re gardless of the ddr6 reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. how- ever, if the interrupt input from the external interrupt (int08 , int09) is enabled, or if the interrupt input of p64/ec1 and p67/trg1 is enabled by the external interrupt control re gister ch. 0 (eic00) of the external interrupt circuit and the interrupt pin selection circuit control register (wicr) of the interrupt pin selection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pul6 register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pul6 register.
mb95630h series document number: 002-04627 rev. *a page 51 of 102 15.4 port f port f is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95630h series hardware manual?. 15.4.1 port f configuration port f is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port f data register (pdrf) ? port f direction register (ddrf) 15.4.2 block diagrams of port f ?pf0/x0 pin this pin has the following peripheral function: ? main clock input oscillation pin (x0) ?pf1/x1 pin this pin has the following peripheral function: ? main clock i/o oscillation pin (x1) ? block diagram of pf0/x0 and pf1/x1 pdrf pin pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 stop mode, watch mode (spl = 1) internal bus hysteresis
mb95630h series document number: 002-04627 rev. *a page 52 of 102 ?pf2/rst pin this pin has the following peripheral function: ? reset pin (rst ) ? block diagram of pf2/rst 15.4.3 port f registers ? port f register functions *: if the pin is an n-ch open drai n pin, the pin state becomes hi-z. ? correspondence between registers and pins for port f *: pf2/rst is the dedicated reset pin on mb95f632h/f633h/f634h/f636h. 15.4.4 port f operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr f register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrf register to external pins. ? if data is written to the pdrf register, the value is stored in the output latch and is outpu t to the pin set as an output port as it is. ? reading the pdrf register returns the pdrf register value. register abbreviation data read read by read-modify-write (rmw) instruction write pdrf 0 pin state is ?l? level. pdrf value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrf value is ?1?. as output port, outputs ?h? level.* ddrf 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name-----pf2*pf1pf0 pdrf -----bit2bit1bit0 ddrf pdrf pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 1 0 stop mode, watch mode (spl = 1) reset input reset input enable reset output enable reset output pin od internal bus hysteresis
mb95630h series document number: 002-04627 rev. *a page 53 of 102 ? operation as an input port ? a pin becomes an input port if the bit in the ddrf register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrf register , the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrf register returns the pin value. howeve r, if the read-modify-write (rmw) type of instruction is used to read the pdrf register, t he pdrf register value is returned. ? operation at reset if the cpu is reset, all bits in the ddrf register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddrf reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. 15.5 port g port g is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of peripheral functions, refer to their respective chapte rs in ?new 8fx mb95630h series hardware manual?. 15.5.1 port g configuration port g is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port g data register (pdrg) ? port g direction register (ddrg) ? port g pull-up register (pulg) 15.5.2 block diagram of port g ? pg1/x0a/sni1 pin this pin has the following peripheral functions: ? subclock input oscillation pin (x0a) ? trigger input pin for the position detection function of the mpg waveform sequencer (sni1) ? pg2/x1a/sni2 pin this pin has the following peripheral functions: ? subclock i/o oscillation pin (x1a) ? trigger input pin for the position detection function of the mpg waveform sequencer (sni2)
mb95630h series document number: 002-04627 rev. *a page 54 of 102 ? block diagram of pg1/x0 a/sni1 and pg2/x1a/sni2 15.5.3 port g registers ? port g register functions ? correspondence between registers and pins for port g 15.5.4 port g operations ? operation as an output port ? a pin becomes an output port if the bit in the ddr g register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs the value of the pdrg regi ster to external pins. register abbreviation data read read by read-modify-write (rmw) instruction write pdrg 0 pin state is ?l? level. pdrg value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrg value is ?1?. as output port, outputs ?h? level. ddrg 0 port input enabled 1 port output enabled pulg 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name-----pg2pg1- pdrg -----bit2bit1- ddrg pulg pdrg pin pdrg read pdrg write executing bit manipulation instruction ddrg read ddrg write pulg read pulg write ddrg pulg 0 1 stop mode, watch mode (spl = 1) peripheral function input hysteresis pull-up internal bus
mb95630h series document number: 002-04627 rev. *a page 55 of 102 ? if data is written to the pdrg register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrg register returns the pdrg register value. ? operation as an input port ? a pin becomes an input port if the bit in the ddrg register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrg register, the value is stored in the output latch but is not output to the pin set as an input port. ? reading the pdrg register returns the pin value. however, if the read-modify-write (rmw) type of instruction is used to read the pdrg register, th e pdrg register va lue is returned. ? operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddrg regist er corresponding to the input pin of a peripheral function to ?0?. ? reading the pdrg register returns the pin value, regardles s of whether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the pdrg register, the pdrg register value is returned. ? operation at reset if the cpu is reset, all bits in the ddrg register are initialized to ?0? and port input is enabled. ? operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or watch mode, the pin is comp ulsorily made to enter th e high impedance state regardless of the ddrg reg- ister value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or that of the peripheral function i/o remains unchanged and the output level is maintained. ? operation of the pull-up register setting the bit in the pulg register to ?1? makes the pull-up resistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regardl ess of the value of the pulg register.
mb95630h series document number: 002-04627 rev. *a page 56 of 102 16. interrupt source table interrupt source interrupt request number vector table address interrupt level setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower register bit external interrupt ch. 0 irq00 0xfffa 0xfffb ilr0 l00 [1:0] high low external interrupt ch. 4 external interrupt ch. 1 irq01 0xfff8 0xfff9 ilr0 l01 [1:0] external interrupt ch. 5 external interrupt ch. 2 irq02 0xfff6 0xfff7 ilr0 l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 0xfff4 0xfff5 ilr0 l03 [1:0] external interrupt ch. 7 uart/sio ch. 0 irq04 0xfff2 0xfff3 ilr1 l04 [1:0] mpg (dtti) 8/16-bit composite timer ch. 0 (lower) irq05 0xfff0 0xfff1 ilr1 l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 0xffee 0xffef ilr1 l06 [1:0] lin-uart (reception) irq07 0xffec 0xffed ilr1 l07 [1:0] lin-uart (transmission) irq08 0xffea 0xffeb ilr2 l08 [1:0] 8/16-bit ppg ch. 1 (lower) irq09 0xffe8 0xffe9 ilr2 l09 [1:0] 8/16-bit ppg ch. 1 (upper) irq10 0xffe6 0xffe7 ilr2 l10 [1:0] 8/16-bit ppg ch. 2 (upper) irq11 0xffe4 0xffe5 ilr2 l11 [1:0] 8/16-bit ppg ch. 0 (upper) irq12 0xffe2 0xffe3 ilr3 l12 [1:0] 8/16-bit ppg ch. 0 (lower) irq13 0xffe0 0xffe1 ilr3 l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 0xffde 0xffdf ilr3 l14 [1:0] 8/16-bit ppg ch. 2 (lower) irq15 0xffdc 0xffdd ilr3 l15 [1:0] 16-bit reload timer ch. 1 irq16 0xffda 0xffdb ilr4 l16 [1:0] mpg (write timing/compare clear) i 2 c bus interface 16-bit ppg timer ch. 1 irq17 0xffd8 0xffd9 ilr4 l17 [1:0] mpg (position detection/compare interrupt) 8/10-bit a/d converter irq18 0xffd6 0xffd7 ilr4 l18 [1:0] time-base timer irq19 0xffd4 0xffd5 ilr4 l19 [1:0] watch prescaler irq20 0xffd2 0xffd3 ilr5 l20 [1:0] comparator external interrupt ch. 8 irq21 0xffd0 0xffd1 ilr5 l21 [1:0] external interrupt ch. 9 8/16-bit composite timer ch. 1 (lower) irq22 0xffce 0xffcf ilr5 l22 [1:0] flash memory irq23 0xffcc 0xffcd ilr5 l23 [1:0]
mb95630h series document number: 002-04627 rev. *a page 57 of 102 17. pin states in each mode pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 pf0/x0 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 4 i/o port* 4 - previous state kept - input blocked* 2 * 4 -hi-z - input blocked* 2 * 4 - previous state kept - input blocked* 2 * 4 -hi-z - input blocked* 2 * 4 -hi-z - input enabled* 1 (however, it does not function.) pf1/x1 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 4 i/o port* 4 - previous state kept - input blocked* 2 * 4 -hi-z - input blocked* 2 * 4 - previous state kept - input blocked* 2 * 4 -hi-z - input blocked* 2 * 4 -hi-z - input enabled* 1 (however, it does not function.) pg1/x0a/ sni1 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 4 / peripheral func- tion i/o i/o port* 4 / peripheral func- tion i/o - previous state kept - input blocked* 2 * 4 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 * 4 - previous state kept - input blocked* 2 * 4 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 * 4 -hi-z - input enabled* 1 (however, it does not function.) pg2/x1a/ sni2 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 4 / peripheral function i/o i/o port* 4 / peripheral function i/o - previous state kept - input blocked* 2 * 4 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 * 4 - previous state kept - input blocked* 2 * 4 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 * 4 -hi-z - input enabled* 1 (however, it does not function.) pf2/rst i/o port reset input reset input reset input reset input reset input reset input* 3 p60/int08/ sda/dtti i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input enabled* 1 (however, it does not function.) p61/int09/ scl/ti1 p62/to10/ ppg00/ opt0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 -hi-z - input enabled* 1 (however, it does not function.) p63/to11/ ppg01/ opt1
mb95630h series document number: 002-04627 rev. *a page 58 of 102 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p64/ec1/ ppg10/ opt2 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input enabled* 1 (however, it does not function.) p65/ppg11/ opt3 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 -hi-z - input enabled* 1 (however, it does not function.) p66/ppg1/ ppg20/ opt4 p67/trg1/ ppg21/ opt5 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input enabled* 1 (however, it does not function.) p10/ppg10/ cmp0_o i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 -hi-z - input enabled* 1 (however, it does not function.) p11/ppg11 p12/dbg/ ec0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input enabled* 1 (however, it does not function.) p13/ppg00 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 -hi-z - input enabled* 1 (however, it does not function.)
mb95630h series document number: 002-04627 rev. *a page 59 of 102 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p14/uck0/ ppg01 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input enabled* 1 (however, it does not function.) p15/uo0/ ppg20 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 -hi-z - input enabled* 1 (however, it does not function.) p16/ui0/ ppg21 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input enabled* 1 (however, it does not function.) p17/to1/ sni0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 - previous state kept - input blocked* 2 - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 -hi-z - input enabled* 1 (however, it does not function.) p00/int00/ an00/ cmp0_p i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input blocked* 2 p01/int01/ an01/ cmp0_n p02/int02/ an02/sck p03/int03/ an03/sot
mb95630h series document number: 002-04627 rev. *a page 60 of 102 spl: pin state setting bit in the standby control register (stbc:spl) hi-z: high impedance *1: ?input enabled? means that the input function is enabled . while the input function is enabled, a pull-up or pull-down operation has to be performed in order to prevent leaks due to external input. if a pin is used as an output port, its pin state is the same as that of other ports. *2: ?input blocked? means direct input ga te operation from the pin is disabled. *3: the pf2/rst pin stays at the state shown w hen configured as a reset pin. *4: the pin stays at the state shown when co nfigured as a general-purpose i/o port. pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p04/int04/ an04/sin/ ec0 i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - previous state kept - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) - hi-z (however, the setting of the pull-up control is effective.) - input blocked* 2 (however, an external interrupt can be input when the external interrupt request is enabled.) -hi-z - input blocked* 2 p05/int05/ an05/to00 p06/int06/ an06/to01 p07/int07/ an07
mb95630h series document number: 002-04627 rev. *a page 61 of 102 18. electrical characteristics 18.1 absolute maximum ratings *1: these parameters are based on the condition that v ss is 0.0 v. *2: v 1 and v 0 must not exceed v cc ? 0.3 v. v 1 must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating. *3: specific pins: p00 to p07, p10, p11, p13 to p17, p62 to p67, pf0, pf1, pg1, pg2 parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ?? 0.3 v ss ? 6v input voltage* 1 v i v ss ?? 0.3 v ss ? 6v*2 output voltage* 1 v o v ss ?? 0.3 v ss ? 6v*2 maximum clamp current i clamp ? 2 ? 2 ma applicable to specific pins* 3 total maximum clamp current ? |i clamp | ? 20 ma applicable to specific pins* 3 ?l? level maximum output current i ol ?15ma ?l? level average current i olav1 ? 4 ma other than p62 to p67 average output current = operating current ? operating ratio (1 pin) i olav2 12 p62 to p67 average output current = operating current ? operating ratio (1 pin) ?l? level total maximum output current ? i ol ? 100 ma ?l? level total average output current ? i olav ?37ma total average output current = operating current ? operating ratio (total number of pins) ?h? level maximum output current i oh ? ? 15 ma ?h? level average current i ohav1 ? ? 4 ma other than p62 to p67 average output current = operating current ? operating ratio (1 pin) i ohav2 ? 8 p62 to p67 average output current = operating current ? operating ratio (1 pin) ?h? level total maximum output current ? i oh ? ? 100 ma ?h? level total average output current ? i ohav ? ? 47 ma total average output current = operating current ? operating ratio (total number of pins) power consumption p d ? 320 mw operating temperature t a ? 40 ? 85 ? c storage temperature t stg ? 55 ? 150 ? c
mb95630h series document number: 002-04627 rev. *a page 62 of 102 ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontro ller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a valu e at which the current to be input to the microcontroller pin when the hv (high voltage) signal is in put is below the standard value, irrespecti ve of whether the current is transient current or stationary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcon troller power supply is off (not fixed at 0 v), since power is supplied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, si nce power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: warning: semiconductor devices may be permanently da maged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolu te maximum ratings. do not exceed any of these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor ? input/output equivalent circuit
mb95630h series document number: 002-04627 rev. *a page 63 of 102 18.2 recommended operating conditions (v ss = 0.0 v) *1: the minimum power supply voltage becomes 2.88 v when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. *2: use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering an unknown mode due to noise, minimize the distan ce between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be und er their recommended op erating condition. operation under any conditio ns other than these conditions may adve rsely affect reliab ility of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4* 1 5.5 v in normal operation 2.3 5.5 hold condition in stop mode decoupling capacitor c s 0.022 1 f *2 operating temperature t a ? 40 ? 85 ? c other than on-chip debug mode ? 5 ? 35 on-chip debug mode c cs dbg * rst ? dbg / rst / c pins connection diagram *: connect the dbg pin to an exte rnal pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not stay at ?l? level until the rese t output is released. the dbg pin becomes a com- munication pin in debug mode. since the actual pull- up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
mb95630h series document number: 002-04627 rev. *a page 64 of 102 18.3 dc characteristics (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85c) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ihi p04, p16, p60, p61 ? 0.7 v cc ?v cc ? 0.3 v cmos input level v ihs p00 to p07, p10 to p17, p60 to p67, pf0, pf1, pg1, pg2 ? 0.8 v cc ?v cc ? 0.3 v hysteresis input v ihm pf2 ? 0.8 v cc ?v cc ? 0.3 v hysteresis input ?l? level input voltage v ili p04, p16, p60, p61 ?v ss ?? 0.3 ? 0.3 v cc v cmos input level v ils p00 to p07, p10 to p17, p60 to p67, pf0, pf1, pg1, pg2 ?v ss ?? 0.3 ? 0.2 v cc v hysteresis input v ilm pf2 ? v ss ?? 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d p12, p60, p61, pf2 ?v ss ?? 0.3 ? vss ? 5.5 v ?h? level output voltage v oh1 output pins other than p12, p62 to p67, pf2 i oh = ? 4 ma v cc ?? 0.5 ? ? v v oh2 p62 to p67 i oh = ? 8 ma v cc ?? 0.5 ? ? v ?l? level output voltage v ol1 output pins other than p62 to p67 i ol = 4 ma ? ? 0.4 v v ol2 p62 to p67 i ol = 12 ma ? ? 0.4 v input leak current (hi-z output leak current) i li all input pins 0.0 v < v i < v cc ? 5? ? 5a when the internal pull-up resistor is disabled internal pull-up resistor r pull p00 to p07, p10, p11, p13 to p17, p62 to p67, pg1, pg2 v i = 0 v 25 50 100 k ? when the internal pull-up resistor is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf
mb95630h series document number: 002-04627 rev. *a page 65 of 102 (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85c) parameter symbol pin name condition value unit remarks min typ* 1 max* 2 power supply current* 3 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?3.65.8ma except during flash memory programming and erasing ?7.513.8ma during flash memory programming and erasing ? 4.1 9.1 ma at a/d conversion i ccs f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?1.3 3ma i ccl f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = ? 25c ? 49 145 a i ccls f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = ? 25c ? 10 15 a in deep standby mode i cct f cl = 32 khz watch mode main stop mode t a = ? 25c ? 7 13 a in deep standby mode i ccmpll v cc f mcrpll = 16 mhz f mp = 16 mhz main cr pll clock mode (multiplied by 4) t a = ? 25c ?4.76.8ma i ccmcr f crh = 4 mhz f mp = 4 mhz main cr clock mode ?1.14.6ma i ccscr sub-cr clock mode (divided by 2) t a = ? 25c ? 58.1 230 a i ccts v cc (external clock operation) f ch = 32 mhz time-base timer mode t a = ? 25c ? 345 395 a in deep standby mode i cch substop mode t a = ? 25c ? 6 10 a in deep standby mode
mb95630h series document number: 002-04627 rev. *a page 66 of 102 (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85c) *1: v cc = 5.0 v, t a = ? 25c *2: v cc = 5.5 v, t a = ? 85c (unless otherwise specified) *3: ? the power supply current is determined by the external clock. when the low-voltage de tection circuit is selected, the power supply current is the sum of adding the curr ent consumption of the low-voltage detection circuit (i lvd ) to one of the values from i cc to i cch . in addition, when both t he low-voltage detection optio n and the cr oscillator are selected, the power supply current is the sum of adding up the current cons umption of the low-voltage detection circuit (i lvd ), the current co nsumption of the cr oscillators (i crh , i crl ) and a specified value. in on-chip debug mode, the cr oscillator (i crh ) and the low-voltage detection circuit are always in operation, and current consumption therefore increases accordingly. ? see ?4. ac characteristics clock timing? for f ch , f cl , f crh and f mcrpll . ? see ?4. ac characteristics so urce clock/machin e clock? for f mp and f mpl . ? the power supply current value in standby mode is meas ured in deep standby mode. the current consumption in normal standby is higher than that in deep standby mode. the power supply current value in normal standby can be found by adding the current consumption differenc e between normal standby mode and deep standby mode (i nstby ) to the power supply current value in deep standby mode. for details of normal standby and deep standby mode, refer to ?chapter 3 clock controller? in ?new 8fx mb95630h series hardware manual?. parameter symbol pin name condition value unit remarks min typ* 1 max* 2 power supply current* 3 i v v cc current consumption of the comparator ?60160a i lvd current consumption of the low-voltage detection circuit ?4 7a i crh current consumption of the main cr oscillator ?240320a i crl current consumption of the sub-cr oscillator oscillating at 100 khz ?720a i nstby current consumption difference between normal standby mode and deep standby mode t a = ? 25c ?2030a
mb95630h series document number: 002-04627 rev. *a page 67 of 102 18.4 ac characteristics 18.4.1 clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40c to ? 85c) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1: open 1 ? 12 mhz when the main external clock is used x0, x1 * 1 ? 32.5 mhz f crh ?? 3.92 4 4.08 mhz operating conditions ? the main cr clock is used. ?0 ? c ?? t a ??? 70 ? c 3.8 4 4.2 mhz operating conditions ? the main cr clock is used. ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c f mcrpll ?? 7.84 8 8.16 mhz operating conditions ? pll multiplication rate: 2 ?0 ? c ?? t a ??? 70 ? c 7.6 8 8.4 mhz operating conditions ? pll multiplication rate: 2 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 9.8 10 10.2 mhz operating conditions ? pll multiplicat ion rate: 2.5 ?0 ? c ?? t a ??? 70 ? c 9.5 10 10.5 mhz operating conditions ? pll multiplicat ion rate: 2.5 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 11.76 12 12.24 mhz operating conditions ? pll multiplication rate: 3 ?0 ? c ?? t a ??? 70 ? c 11.4 12 12.6 mhz operating conditions ? pll multiplication rate: 3 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 15.68 16 16.32 mhz operating conditions ? pll multiplication rate: 4 ?0 ? c ?? t a ??? 70 ? c 15.2 16 16.8 mhz operating conditions ? pll multiplication rate: 4 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c f cl x0a, x1a ? ? 32.768 ? khz when the suboscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 150 khz when the sub-cr clock is used
mb95630h series document number: 002-04627 rev. *a page 68 of 102 (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40c to ? 85c) *: the external clock signal is input to x0 and the inverted external clock signal to x1. parameter symbol pin name condition value unit remarks min typ max clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1: open 83.4 ? 1000 ns when an external clock is used x0, x1 * 30.8 ? 1000 ns t lcyl x0a, x1a ?? 30.5 ? s when the subclock is used input clock pulse width t wh1 , t wl1 x0 x1: open 33.4 ?? ns when an external clock is used, the duty ratio should range between 40% and 60%. x0, x1 * 12.4 ?? ns t wh2 , t wl2 x0a ? ?15.2 ? s input clock rising time and falling time t cr , t cf x0, x0a x1: open ? ? 5ns when an external clock is used x0, x1, x0a, x1a *??5ns cr oscillation start time t crhwk ????50s when the main cr clock is used t crlwk ????30s when the sub-cr clock is used pll oscillation start time t mcrpllwk ????100s when the main cr pll clock is used x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf ? input waveform generated when an external clock (main clock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0 x1 x0 x1 f ch f ch when an external clock is used (x1 is open) x0 x1 open f ch ? figure of main clock inpu t port external connection
mb95630h series document number: 002-04627 rev. *a page 69 of 102 x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf ? input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0a x1a x0a x1a open f cl f cl ? figure of subclock input port external connection t crhwk 1/f crh main cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr clock) is used t crlwk 1/f crl sub-cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (sub-cr clock) is used
mb95630h series document number: 002-04627 rev. *a page 70 of 102 18.4.2 source clock/machine clock (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 62.5 ? 250 ns when the main cr clock is used min: f crh = 4 mhz, multiplied by 4 max: f crh = 4 mhz, no division ?61?s when the suboscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f cl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used ? 4 ? mhz when the main cr clock is used f spl ? 16.384 ? khz when the subo scillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 250 ? 4000 ns when the main cr clock is used min: f sp = 4 mhz, no division max: f sp = 4 mhz, divided by 16 61 ? 976.5 s when the suboscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 t mcrpllwk 1/f mcrpll main cr pll clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr pll clock) is used
mb95630h series document number: 002-04627 rev. *a page 71 of 102 *1: this is the clock before it is divided according to the di vision ratio set by the machine cl ock division ratio select bits (sycc:div[1:0]). this source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (sycc:div[1:0]). in addit ion, a source clock can be selected from the follow- ing. ? main clock divided by 2 ? main cr clock ? pll multiplication of main cr clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontrolle r. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.25 ? 16 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the s uboscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz parameter symbol pin name value unit remarks min typ max f ch (main oscillation clock) divided by 2 divided by 2 divided by 2 f mcrpll (main cr pll clock) f crh (main cr clock) f cl (suboscillation clock) f crl (sub-cr clock) sclk (source clock) mclk (machine clock) machine clock divide ratio select bits (sycc:div[1:0]) clock mode select bits (sycc:scs[2:0]) division circuit 1 1/4 1/8 1/16 ? schematic diagram of the clock generation block
mb95630h series document number: 002-04627 rev. *a page 72 of 102 18.4.3 external reset (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *: see ?source clock/machine clock? for t mclk . parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * ? ns operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.7 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) ? operating voltage - operating frequency (t a = ? 40c to ? 85c) 0.2 v cc rst 0.2 v cc t rstl
mb95630h series document number: 002-04627 rev. *a page 73 of 102 18.4.4 power-on reset (v ss = 0.0 v, t a = ? 40c to ? 85c) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. 18.4.5 peripheral input timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *: see ?source clock/machine clock? for t mclk . parameter symbol condition value unit remarks min max power supply rising time t r ?? 50 ms power supply cutoff time t off ? 1 ? ms wait time until power-on parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int09, ec0, ec1, ti1, trg1 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode set the slope of rising to a value below 30 mv/ms. int00 to int09, ec0, ec1, ti1, trg1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
mb95630h series document number: 002-04627 rev. *a page 74 of 102 18.4.6 lin-uart timing sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is disabled* 2 . (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t slovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivshi sck, sin t mclk * 3 ? 80 ? ns sck ? ? valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin: c l = 80 pf ? 1 ttl 3 t mclk * 3 ? t r ?ns serial clock ?h? pulse width t shsl sck t mclk * 3 ? 10 ? ns sck ? ? sot delay time t slove sck, sot ? 2 t mclk * 3 ? 60 ns valid sin ? sck ? t ivshe sck, sin 30 ? ns sck ? ? valid sin hold time t shixe sck, sin t mclk * 3 ? 30 ? ns sck falling time t f sck ? 10 ns sck rising time t r sck ? 10 ns 0.2 v cc 0.2 v cc 0.8 v cc t slovi t ivshi t shixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode
mb95630h series document number: 002-04627 rev. *a page 75 of 102 sampling is executed at the falling edge of the sampling clock* 1 , and serial clock delay is disabled* 2 . (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t shovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivsli sck, sin t mclk * 3 ? 80 ? ns sck ?? valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin: c l = 80 pf ? 1 ttl 3 t mclk * 3 ?? t r ?ns serial clock ?l? pulse width t slsh sck t mclk * 3 ? 10 ? ns sck ? ? sot delay time t shove sck, sot ? 2 t mclk * 3 ? 60 ns valid sin ? sck ? t ivsle sck, sin 30 ? ns sck ?? valid sin hold time t slixe sck, sin t mclk * 3 ? 30 ? ns sck falling time t f sck ? 10 ns sck rising time t r sck ? 10 ns 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slove t ivshe t shixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t slsh t shsl t r 0.8 v cc t f ? external shift clock mode
mb95630h series document number: 002-04627 rev. *a page 76 of 102 0.2 v cc 0.8 v cc 0.8 v cc t shovi t ivsli t slixi 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc t shove t ivsle t slixe 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t shsl t slsh t f 0.8 v cc t r ? external shift clock mode
mb95630h series document number: 002-04627 rev. *a page 77 of 102 sampling is executed at the rising edge of the sampling clock* 1 , and serial clock delay is enabled* 2 . (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . sampling is executed at the falling edge of the sampling clock* 1 , and serial clock delay is enabled* 2 . (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *1: there is a function used to choose whether the sampling of reception data is performed at a ri sing edge or a falling edge of the serial clock. *2: the serial clock delay function is a function used to dela y the output signal of the serial clock for half the clock. *3: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ??? sot delay time t shovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivsli sck, sin t mclk * 3 ? 80 ? ns sck ?? valid sin hold time t slixi sck, sin 0 ? ns sot ? sck ? delay time t sovli sck, sot 3t mclk * 3 ?? 70 ? ns parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck internal clock operation output pin: c l = 80 pf ? 1 ttl 5 t mclk * 3 ?ns sck ? ? sot delay time t slovi sck, sot ? 50 ? 50 ns valid sin ? sck ? t ivshi sck, sin t mclk * 3 ? 80 ? ns sck ? ? valid sin hold time t shixi sck, sin 0 ? ns sot ? sck ? delay time t sovhi sck, sot 3t mclk * 3 ?? 70 ? ns 0.8 v cc 0.2 v cc 0.2 v cc t shovi t sovli t ivsli t slixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc
mb95630h series document number: 002-04627 rev. *a page 78 of 102 18.4.7 low-voltage detection (v ss = 0.0 v, t a = ? 40c to ? 85c) *: the release voltage and the detection voltage can be sele cted by using the lvd reset voltage selection id register (lvdr) in the low-voltage detection reset circuit. for details of the lvdr register, refer to ?chapter 16 low- voltage detection reset circuit? in ?new 8fx mb95630h series hardware manual?. parameter symbol value unit remarks min typ max release voltage* v dl ? 2.52 2.7 2.88 v at power supply rise 2.61 2.8 2.99 2.89 3.1 3.31 3.08 3.3 3.52 detection voltage* v dl ? 2.43 2.6 2.77 v at power supply fall 2.52 2.7 2.88 2.80 3 3.20 2.99 3.2 3.41 hysteresis width v hys ??100mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 650 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 650 ? ? s slope of power supply that the reset detection signal generates within the rating (v dl- ) reset release delay time t d1 ??30s reset detection delay time t d2 ??30s lvd reset threshold voltage transition stabilization time t stb 10 ? ? s 0.2 v cc 0.8 v cc 0.8 v cc t slovi t sovhi t ivshi t shixi 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc
mb95630h series document number: 002-04627 rev. *a page 79 of 102 v hys t d2 t d1 t r t f v cc v on v off v dl+ v dl- time time internal reset signal
mb95630h series document number: 002-04627 rev. *a page 80 of 102 18.4.8 i 2 c bus interface timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: the maximum t hd;dat in the standard-mode is applicab le only when the time during which the device is holding the scl signal at ?l? (t low ) does not extend. *3: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, provided that the condition of t su;dat ? 250 ns is fulfilled. parameter symbol pin name condition value unit standard- mode fast-mode min max min max scl clock frequency f scl scl r = 1.7 k ? , c = 50 pf* 1 01000400khz (repeated) start condition hold time sda ??? scl ? t hd;sta scl, sda 4.0 ? 0.6 ? s scl clock ?l? width t low scl 4.7 ? 1.3 ? s scl clock ?h? width t high scl 4.0 ? 0.6 ? s (repeated) start condition setup time scl ??? sda ? t su;sta scl, sda 4.7 ? 0.6 ? s data hold time scl ??? sda ?? t hd;dat scl, sda 0 3.45 *2 00.9 *3 s data setup time sda ???? scl ? t su;dat scl, sda 0.25 ? 0.1 ? s stop condition setup time scl ? ? sda ? t su;sto scl, sda 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl, sda 4.7 ? 1.3 ? s sda scl t wakeup t hd;sta t su;dat f scl t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
mb95630h series document number: 002-04627 rev. *a page 81 of 102 (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) parameter symbol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k ? , c = 50 pf* 1 (2 ? nm/2)t mclk ? 20 ? ns master mode scl clock ?h? width t high scl (nm/2)t mclk ? 20 (nm/2)t mclk ? 20 ns master mode start condition hold time t hd;sta scl, sda (-1 ? nm/2)t mclk ? 20 (-1 ? nm)t mclk ? 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl, sda (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode start condition setup time t su;sta scl, sda (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode bus free time between stop condition and start condition t buf scl, sda (2 nm ? 4) t mclk ? 20 ? ns data hold time t hd;dat scl, sda 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl, sda (-2 ? nm/2) t mclk ? 20 (-1 ? nm/2) t mclk ? 20 ns master mode it is assumed that ?l? of scl is not extended. the minimum value is applied to the first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl (nm/2) t mclk ? 20 (1 ? nm/2) t mclk ? 20 ns the minimum value is applied to the interrupt at the ninth scl ? . the maximum value is applied to the interrupt at the eighth scl ? . scl clock ?l? width t low scl 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl 4 t mclk ? 20 ? ns at reception
mb95630h series document number: 002-04627 rev. *a page 82 of 102 (continued) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: ? see ?source clock/machine clock? for t mclk . ? m represents the cs[4:3] bits in the i 2 c clock control register ch. 0 (iccr0). ? n represents the cs[2:0] bits in the i 2 c clock control register ch. 0 (iccr0). ? the actual timing of the i 2 c bus interface is determined by the val ues of m and n set by the machine clock (t mclk ) and the cs[4:0] bits in the iccr0 register. ? standard-mode: m and n can be set to values in the following range: 0.9 mhz ? t mclk (machine clock) ? 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 mhz < t mclk ? 1 mhz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 mhz < t mclk ? 2 mhz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 mhz < t mclk ? 4 mhz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 mhz < t mclk ? 10 mhz (m, n) = (8, 22) : 0.9 mhz < t mclk ? 16.25 mhz ? fast-mode: m and n can be set to values in the following range: 3.3 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are determ ined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 mhz < t mclk ? 4 mhz (m, n) = (1, 22), (5, 4) : 3.3 mhz < t mclk ? 8 mhz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 mhz < t mclk ? 10 mhz (m, n) = (5, 8) : 3.3 mhz < t mclk ? 16.25 mhz parameter symbol pin name condition value* 2 unit remarks min max start condition detection t hd;sta scl, sda r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns no start condition is detected when 1 t mclk is used at reception. stop condition detection t su;sto scl, sda 2 t mclk ? 20 ? ns no stop condition is detected when 1 t mclk is used at reception. restart condition detection condition t su;sta scl, sda 2 t mclk ? 20 ? ns no restart condition is detected when 1 t mclk is used at reception. bus free time t buf scl, sda 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl, sda 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl, sda t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl, sda 0 ? ns at reception data setup time t su;dat scl, sda t mclk ? 20 ? ns at reception sda ? ? scl ? (with wakeup function in use) t wakeup scl, sda oscillation stabilization wait time ? 2 t mclk ? 20 ?ns
mb95630h series document number: 002-04627 rev. *a page 83 of 102 18.4.9 uart/sio, serial i/o timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) *: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck0 internal clock operation 4 t mclk *? ns uck ??? uo time t slov uck0, uo0 ? 190 ? 190 ns valid ui ? uck ? t ivsh uck0, ui0 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, ui0 2 t mclk *? ns serial clock ?h? pulse width t shsl uck0 external clock operation 4 t mclk *? ns serial clock ?l? pulse width t slsh uck0 4 t mclk *? ns uck ??? uo time t slov uck0, uo0 ? 190 ns valid ui ? uck ? t ivsh uck0, ui0 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, ui0 2 t mclk *? ns 0.2 v cc 0.2 v cc 0.8 v cc t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0 uo0 ui0 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode
mb95630h series document number: 002-04627 rev. *a page 84 of 102 18.4.10 mpg input timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40c to ? 85c) 18.4.11 comparator timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40c to ? 85c) parameter symbol pin name condition value unit remarks min max input pulse width t tiwh , t tiwl sni0 to sni2, dtti ?4 t mclk ?ns parameter pin name value unit remarks min typ max voltage range cmp0_p, cmp0_n 0?v cc ? 1.3 v offset voltage cmp0_p, cmp0_n ? 15 ? ? 15 mv delay time cmp0_o ? 650 1200 ns overdrive 5 mv ? 140 420 ns overdrive 50 mv power down delay cmp0_o ? ? 1200 ns power down recovery pd: 1 ? 0 power up stabilization time cmp0_o ? ? 1200 ns output stabilization time at power up t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0 uo0 ui0 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slsh t shsl ? external shift clock mode 0.8 v cc sni0 to sni2, dtti 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl
mb95630h series document number: 002-04627 rev. *a page 85 of 102 18.5 a/d converter 18.5.1 a/d converter electrical characteristics (v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ? 40c to ? 85c) 18.5.2 notes on using a/d converter ? external impedance of analog input and its sampling time the a/d converter of the mb95630h series has a sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision stan- dard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the exte rnal impedance so that the sampling time is longer than the minimum value. in addition, if suff icient sampling time cannot be secured, connect a capacitor of about 0.1 f to the analog input pin. parameter symbol value unit remarks min typ max resolution ? ??10bit to t a l e r r o r ? 3? ? 3lsb linearity error ? 2.5 ? ? 2.5 lsb differential linearity error ? 1.9 ? ? 1.9 lsb zero transition voltage v 0t v ss ?? 1.5 lsb v ss ? 0.5 lsb v ss ? 2.5 lsb v full-scale transition voltage v fst v cc ?? 4.5 lsb v cc ?? 2 lsb v cc ? 0.5 lsb v compare time ? 3 ? 10 s 2.7 v ? v cc ? 5.5 v sampling time ? 0.941 ? ? s 2.7 v ? v cc ? 5.5 v, with external impedance ? 3.3 k ? and external capacitance = 10 pf analog input current i ain ? 0.3 ? ? 0.3 a analog input voltage v ain v ss ?v cc v note: the values are reference values. 4.5 v v cc 5.5 v 2.7 v v cc < 4.5 v 1.45 k (max) 2.7 k (max) 14.89 pf (max) v cc r c 14.89 pf (max) comparator analog input during sampling: on r c ? analog input equivalent circuit
mb95630h series document number: 002-04627 rev. *a page 86 of 102 ? a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. [external impedance = 0 k to 100 k ] external impedance [k ] minimum sampling time [ s] 02468101214161820 100 80 60 40 20 0 [external impedance = 0 k to 20 k ] external impedance [k ] minimum sampling time [ s] 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 20 15 10 5 0 note: external capacitance = 10 pf ? relationship between external impedance and minimum sampling time
mb95630h series document number: 002-04627 rev. *a page 87 of 102 18.5.3 definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (?0000000000? ? ? ?0000000001?) of a device to the full-scale transition point (?1111111111? ? ? ?1111111110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to change the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a th eoretical value. the error ca n be caused by a zero tran- sition error, a full-scale transition errors, a linearity error, a quantum error, or noise. v fst ideal i/o characteristics 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff digital output digital output 2 lsb v 0t 1 lsb 0.5 lsb total error analog input analog input 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn {1 lsb (n ? 1) + 0.5 lsb} v nt total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb lsb = v cc ? v ss 1024 v 1 lsb = v ss v cc v ss v cc
mb95630h series document number: 002-04627 rev. *a page 88 of 102 zero transition error linearity error full-scale transition error 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff digital output differential linearity error of digital output n v (n + 1)t ? v nt 1 lsb ? 1 = linearity error of digital output n v nt ? {1 lsb n + v 0t } 1 lsb = digital output analog input 0x001 0x002 0x3fc 0x3fd 0x003 0x3fe 0x3ff 0x004 actual conversion characteristic actual conversion characteristic v 0t (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc v ss v cc v ss v cc v ss v cc analog input digital output analog input ideal characteristic {1 lsb n + v 0t } actual conversion characteristic ideal characteristic actual conversion characteristic v 0t (measurement value) v fst (measurement value) v nt differential linearity error 0x(n ? 2) 0x(n ? 1) 0xn 0x(n + 1) digital output analog input actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n + 1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n ? 1) to 0xn v 0t (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc ? 2 lsb [v] ideal characteristic
mb95630h series document number: 002-04627 rev. *a page 89 of 102 18.6 flash memory program/erase characteristics *1: v cc = 5.5 v, t a = ? 25c, 0 cycle *2: v cc = 2.4 v, t a = ? 85c, 100000 cycles *3: these values were converted from the result of a techno logy reliability assessment. (t hese values were converted from the result of a high temperature accelerated test us ing the arrhenius equation with the average temperature being ? 85c.) parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.3* 1 1.6* 2 s the time of writing ?0x00? prior to erasure is excluded. sector erase time (32 kbyte sector) ?0.6* 1 3.1* 2 s the time of writing ?0x00? prior to erasure is excluded. byte writing time ? 17 272 s system-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 2.4 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = ? 85c number of program/erase cycles: 1000 or below 10* 3 ?? average t a = ? 85c number of program/erase cycles: 1001 to 10000 inclusive 5* 3 ?? average t a = ? 85c number of program/erase cycles: 10001 or above
mb95630h series document number: 002-04627 rev. *a page 90 of 102 19. sample characteristics ? power supply current temp erature characteristics 0 5 10 15 1234567 i cc [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i cc ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the external clock operating 0 5 10 15 ? 50 0 + 50 + 100 + 150 i cc [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 2 1 3 4 5 6 1234567 i ccs [ma] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 2 1 3 4 5 6 ? 50 0 ? 50 + 100 + 150 i ccs [ma] t a [ c] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 20 80 60 40 140 120 100 1234567 i ccl [ a] v cc [v] 0 20 80 60 40 140 120 100 ? 50 0 + 50 + 100 + 150 i ccl [ a] t a [ c] i cc ? t a v cc ? 5.5 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main clock mode with the ex ternal clock operating i ccs ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccs ? t a v cc ? 5.5 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) main sleep mode with the external clock operating i ccl ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) subclock mode with the external clock operating i ccl ? t a v cc ? 5.5 v, f mpl ? 16 khz (divided by 2) subclock mode with the external clock operating
mb95630h series document number: 002-04627 rev. *a page 91 of 102 0 2 8 6 4 20 18 16 14 12 10 ? 50 0 + 50 + 100 + 150 i cct [ a] t a [ c] i cct ? t a v cc ? 5.5 v, f mpl ? 16 khz (divided by 2) watch mode with the external clock operating 0 10 20 30 ? 50 0 + 50 + 100 + 150 i ccls [ a] t a [ c] i ccls ? t a v cc ? 5.5 v, f mpl ? 16 khz (divided by 2) subsleep mode with the external clock operating 0 10 20 30 1234567 i ccls [ a] v cc [v] 0 2 8 6 4 20 18 16 14 12 10 1234567 i cct [ a] v cc [v] 0 200 100 300 400 500 600 1234567 i ccts [ a] v cc [v] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz 0 200 100 300 400 500 600 ? 50 0 + 50 + 100 + 150 i ccts [ a] t a [ c] f mp = 16 mhz f mp = 10 mhz f mp = 8 mhz f mp = 4 mhz f mp = 2 mhz i ccls ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) subsleep mode with the external clock operating i cct ? v cc t a ? ? 25 ? c, f mpl ? 16 khz (divided by 2) watch mode with the external clock operating i ccts ? v cc t a ? ? 25 ? c, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating i ccts ? t a v cc ? 5.5 v, f mp ? 2, 4, 8, 10, 16 mhz (divided by 2) time-base timer mode with the external clock operating
mb95630h series document number: 002-04627 rev. *a page 92 of 102 0 8 4 12 16 20 ? 50 0 + 50 + 100 + 150 i cch [ a] t a [ c] i cch ? t a v cc ? 5.5 v, f mpl ? (stop) substop mode with the external clock stopping 0 8 4 12 16 20 1234567 i cch [ a] v cc [v] 0 8 6 4 2 10 1234567 i ccmcr [ma] v cc [v] 0 8 6 4 2 10 ? 50 0 + 50 + 100 + 150 i ccmcr [ma] t a [ c] 0 8 6 4 2 10 1234567 i ccmpll [ma] v cc [v] 0 8 6 4 2 10 ? 50 0 + 50 + 100 + 150 i ccmpll [ma] t a [ c] i cch ? v cc t a ? ? 25 ? c, f mpl ? (stop) substop mode with the external clock stopping i ccmcr ? v cc t a ? ? 25 ? c, f mp ? 4 mhz (no division) main cr clock mode i ccmcr ? t a v cc ? 5.5 v, f mp ? 4 mhz (no division) main cr clock mode i ccmpll ? v cc t a ? ? 25 ? c, f mp ? 16 mhz (pll multiplication rate: 4) main cr pll clock mode i ccmpll ? t a v cc ? 5.5 v, f mp ? 16 mhz (pll mult iplication rate: 4) main cr pll clock mode
mb95630h series document number: 002-04627 rev. *a page 93 of 102 0 150 100 50 200 ? 50 0 + 50 + 100 + 150 i ccscr [ a] t a [ c] i ccscr ? t a v cc ? 5.5 v, f mpl ? 50 khz (divided by 2) sub-cr clock mode 0 150 100 50 200 1234567 i ccscr [ a] v cc [v] i ccscr ? v cc t a ? ? 25 ? c, f mpl ? 50 khz (divided by 2) sub-cr clock mode
mb95630h series document number: 002-04627 rev. *a page 94 of 102 ? input voltage characteristics 0 1 2 4 5 234567 v ihi /v ili [v] v cc [v] 3 v ihi v ili 0 1 2 4 5 234567 v ihs /v ils [v] v cc [v] 3 v ihs v ils v ihi ? v cc and v ili ? v cc t a ? ? 25 ? c v ihs ? v cc and v ils ? v cc t a ? ? 25 ? c 0 1 2 4 5 234567 v ihm /v ilm [v] v cc [v] 3 v ihm v ilm v ihm ? v cc and v ilm ? v cc t a ? ? 25 ? c
mb95630h series document number: 002-04627 rev. *a page 95 of 102 ? output voltage characteristics 0.0 0.2 0.4 0.8 1.4 1.2 1.0 0 ? 2 ? 1 ? 3 ? 5 ? 7 ? 9 ? 4 ? 6 ? 8 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 v cc ? v oh2 [v] i oh [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh2 ) ? i oh t a ? ? 25 ? c v ol1 ? i ol t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.4 1.2 1.0 0 ? 2 ? 1 ? 3 ? 5 ? 7 ? 9 ? 4 ? 6 ? 8 ? 10 ? 11 ? 12 ? 13 ? 14 ? 15 v cc ? v oh1 [v] i oh [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v (v cc ? v oh1 ) ? i oh t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.0 02 13579 4 6 8 101112131415 v ol2 [v] i ol [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v ol2 ? i ol t a ? ? 25 ? c 0.0 0.2 0.4 0.8 1.4 1.2 1.0 02 13579 4 6 8 101112131415 v ol1 [v] i ol [ma] 0.6 v cc = 2.4 v v cc = 2.7 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v
mb95630h series document number: 002-04627 rev. *a page 96 of 102 ? pull-up characteristics 0 50 100 150 200 123456 r pull [k ] v cc [v] r pull ? v cc t a ? ? 25 ? c
mb95630h series document number: 002-04627 rev. *a page 97 of 102 20. mask options 21. ordering information no. part number mb95f632h mb95f633h mb95f634h mb95f636h mb95f632k mb95f633k mb95f634k mb95f636k selectable/fixed fixed 1 low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset with dedicated reset input without dedicated reset input part number package mb95f632hpmc-g-sne2 mb95f632kpmc-g-sne2 mb95f633hpmc-g-sne2 mb95f633kpmc-g-sne2 mb95f634hpmc-g-sne2 mb95f634kpmc-g-sne2 mb95f636hpmc-g-sne2 mb95f636kpmc-g-sne2 mb95f636kpmc-g-une2 32-pin plastic lqfp (fpt-32p-m30) mb95f632hp-g-sh-sne2 mb95f632kp-g-sh-sne2 mb95f633hp-g-sh-sne2 mb95f633kp-g-sh-sne2 mb95f634hp-g-sh-sne2 mb95f634kp-g-sh-sne2 mb95f636hp-g-sh-sne2 mb95f636kp-g-sh-sne2 32-pin plastic sh-dip (dip-32p-m06) mb95f632hwqn-g-sne1 mb95f632kwqn-g-sne1 MB95F633HWQN-G-SNE1 mb95f633kwqn-g-sne1 mb95f634hwqn-g-sne1 mb95f634kwqn-g-sne1 mb95f636hwqn-g-sne1 mb95f636kwqn-g-sne1 32-pin plastic qfn (lcc-32p-m19)
mb95630h series document number: 002-04627 rev. *a page 98 of 102 22. package dimension 32-pin plastic lqfp lead pitch 0.80 mm package width package length 7.00 mm 7.00 mm lead shape gullwing sealing method plastic mold mounting height 1.60 mm max 32-pin plastic lqfp (fpt-32p-m30) (fpt-32p-m30) c 7.000.10(.276.004)sq 0.80(.031) "a" 0.10(.004) 9.000.20(.354.008)sq 18 17 24 9 16 25 32 index 0~7 0.600.15 (.024.006) 0.25(.010) 0.100.05 (.004.002) details of "a" part 0.10(.004) * 2009-2010 fujitsu semiconductor limited f32051s-c-1-2 0.20(.008) m 0.35 +0.08 ? 0.03 +.003 ? .001 .014 0.13 +0.05 ? 0.00 +.002 ? .000 .005 (.063) max 1.60 max (mounting height) dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mb95630h series document number: 002-04627 rev. *a page 99 of 102 32-pin plastic sdip lead pitch 1.778 mm low space 10.16 mm sealing method plastic mold 32-pin plastic sdip (dip-32p-m06) (dip-32p-m06) c 2003-2010 fujitsu semiconductor limited d32018s-c-1-3 (.350 .010) *8.89 0.25 1.778(.070) 1.27(.050) 10.16(.400) index *28.00 1.102 +0.20 ? 0.30 ? .012 +.008 4.70 .185 +0.70 ? 0.20 ? .008 +.028 3.30 .130 +0.20 ? 0.30 ? .012 +.008 max. 1.02 .040 ? 0.20 ? .008 +.012 +0.30 min. 0.51(.020) 0~15 m 0.25(.010) .019 0.48 +0.08 +.003 ? .005 ? 0.12 0.27 .011 ? .003 ? 0.07 +.001 +0.03 dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness.
mb95630h series document number: 002-04627 rev. *a page 100 of 102 32-pin plastic qfn lead pitch 0.50 mm package width package length 5.00 mm 5.00 mm sealing method plastic mold mounting height 0.80 mm max weight 0.06 g 32-pin plastic qfn (lcc-32p-m19) (lcc-32p-m19) (.010 ) c 2009-2010 fujitsu semiconductor limited c32071s-c-1-2 (.197 .004) 5.00 0.10 5.00 0.10 (.197 .004) (3-r0.20) ((3-r.008)) 0.50(.020) 1pin corner (c0.30(c.012)) 0.75 0.05 (0.20(.008)) index area 0.40 0.05 (.016 .002) +0.03 ? 0.02 ? .001 +.001 0.02 (.001 ) (.138 .004) 3.50 0.10 3.50 0.10 (.138 .004) (typ) (.030 .002) +0.05 ? 0.07 ? .003 +.002 0.25 dimensions in mm (inches). note: the values in parentheses are reference values.
mb95630h series document number: 002-04627 rev. *a page 101 of 102 23. major changes in this edition spansion publication number: ds702-00009-3v0-e note: please see ?document history ? about later revised information. document history page page section details 22 pin connection ?c pin corrected the fo llowing statement. the bypass capacitor for the v cc pin must have a capacitance larger than c s . ? the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . 66 electrical characteristics 2. recommended operating conditions corrected the following st atement in remark *2. the bypass capacitor for the v cc pin must have a capacitance larger than c s . ? the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . 71 4. ac characteristics (1) clock timing corrected the pin names of the parameter ?input clock rising time and falling time?. x0 ? x0, x0a x0, x1 ? x0, x1, x0a, x1a document title: mb95630h series, new 8fx 8-bit microcontrollers document number: 002-04627 revision ecn orig. of change submission date description of change ** - akih 06/07/2013 migrated to cypress and assigned document number 002-04627. no change to document contents or format. *a 5193921 akih 03/29/2016 updated to cypress template added ?mb95f636kpmc-g-une2? in ?ordering information?
document number: 002-04627 rev. *a revised march 29, 2016 page 102 of 102 mb95630h series ? cypress semiconductor corporation 2011-2016. this document is the property of cypress semiconductor corporation and its subsi diaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you under its copyright rights in the software, a personal, non-exclusive, nontransferable license (without the r ight to sublicense) (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units. cypress also gran ts you a personal, non-exclusive, nontransferable, license (without the right to sublicense) under those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely to the minimum extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. any oth er use, reproduction, modification, translation, or compilation of the software is prohibited. cypress makes no warranty of any kind, express or implied, with regard to this document or any software, including, but not lim ited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any informati on provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly d esign, program, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as crit ical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support de vices or systems, other medical devices or systems (including r esuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or syste m, or to affect its safety or effectiv eness. cypress is not liable, in whole or in part, and company shall and hereby does release cypress from any claim, damage, or other liability arising from or relate d to all unintended uses of cypress products. company shall indemnify and hold cypress harmless from and against all claims, costs, da mages, and other liabilities, including claims for personal inj ury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypr ess trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s represent atives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions cypress.com/psoc psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/support

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